Image coding apparatus

Claim 2

An image coding apparatus for sequentially coding an input image signal, which is supplied at a predetermined frame rate, at a rate that is independent of said frame rate and for obtaining a coding image signal for transmission from which frames are thinned out, comprising: a frame memory having a recording area corresponding to one frame of the input image signal to store said input image signal; a write address generator to sequentially generate write addresses in the frame memory in correspondence to said input image signal; coding means for executing a coding process by using a signal which is read out from the frame memory and for generating a frame change request; a read address generator to sequentially generate read addresses in the frame memory in response to said frame change request; and write limiting means for comparing said write addresses and said read addresses, for stopping a subsequent writing operation of the image signal frame written in the frame memory when a particular write address approaches a particular read address, and for restarting the writing operation from the head of the next frame.

Claim 3

An apparatus according to claim 1, further comprising reading operation delay means for delaying said frame change request and transferring operation to the read address generator when said particular write address is located within a predetermined range from the head of the frame when the frame change request is generated.

Claim 4

An image coding apparatus in which an input image signal that is supplied at a predetermined frame rate in accordance with a sequence of image scanning lines whose horizontal scan has priority over the vertical scan is sequentially coded at a rate that is independent of said frame rate, to thereby obtain a coded image signal for transmission from which frames are thinned out, comprising: a frame memory having a memory area corresponding to one frame of said input image signal that is specified by horizontal and vertical two-dimensional addresses for storing said input image signal; a write address generator for sequentially generating write addresses in the frame memory in accordance with said sequence of image scanning lines of said input image signal; coding means for executing a coding process using a signal which is read out from the frame memory and for generating a frame change request; a read address generator for sequentially generate read addresses in the frame memory in response to said frame change request; and write limiting means for comparing said write addresses and said read addresses, for stopping subsequent writing operation of frames written in the frame memory when a particular write address approaches a particular read address, and for restarting the writing operation from the head of the next frame.

Claim 5

An image coding apparatus in which an input image signal that is supplied at a predetermined frame rate in accordance with a sequence of image scanning lines whose horizontal scan has priority over the vertical scan is sequentially coded at a rate that is independent of said frame rate, to thereby obtain a coded image signal for transmission from which frames are thinned out, comprising: a frame memory having a memory area corresponding to one frame of said input image signal that is specified by horizontal and vertical two-dimensional addresses for storing said input image signal; a write address generator for sequentially generating write addresses in the frame memory in accordance with said sequence of image scanning lines of said input image signal; coding means for executing a coding process using a signal which is read out from the frame memory and for generating a frame change request; a read address generator for sequentially generate read addresses in the frame memory in response to said frame change request; and write limiting means for comparing said write addresses and said read addresses, for stopping subsequent writing operation of frames written in the frame memory when a particular write address approaches a particular read address, and for restarting the writing operation from the head of the next frame.

Claim 6

An apparatus according to claim 3, wherein the write limiting means compares a vertical address of said particular write address and a vertical address of said particular read address.

Claim 7

An apparatus according to claim 3, wherein the write limiting means compares a value which is obtained by converting said particular write address into a one-dimensional address and a value which is obtained by converting said particular read address into a one-dimensional address.

Claim 8

An apparatus according to claim 3, further comprising reading operation delay means for delaying said frame change request and for transferring operation to said read address generator when said particular write address is located within a predetermined range from the head of the frame when the frame change request is generated.

Claim 9

An apparatus according to claim 6, wherein said reading operation delay means delays said frame change request when a vertical address of said particular write address is located within a predetermined range from the head of the frame.

Claim 10

An image coding apparatus for sequentially coding an input image signal, which is supplied at a predetermined frame rate, at a rate that is independent of said frame rate, thereby obtaining a coding image signal for transmission from which frames are thinned out. comprising: first and second frame memories, each having a recording area, corresponding to one frame of the input image signal, for storing the input image signal; coding means for executing a coding process by using both the input image signal which is read out from one of the first and second frame memories and a reference signal which is read out from the other one of the first and second frame memories; decoding means for decoding a coded image signal from said coding means; signal path change means for allowing the first and second frame memories to alternately execute a first operation for reading out the stored input image signal and supplying said read out signal to said coding means and writing the decoded image signal which is generated from said decoding means, and for reading out the stored decoded image signal as a reference signal and supplying said decoded signal to said coding means and writing the input image signal in response to the frame change request which is generated from said coding means; and write limiting means, provided for each of the first and second frame memories, for stopping a subsequent writing operation of the frames written when a write address of the input image signal in said second operation approaches a read address of the reference signal and for restarting the writing operation from the head of the next frame.

Claim 11

An image coding apparatus for sequentially coding an input image signal, which is supplied at a predetermined frame rate, at a rate that is independent of said frame rate, thereby obtaining a coding image signal for transmission from which frames are thinned out. comprising: first and second frame memories, each having a recording area, corresponding to one frame of the input image signal, for storing the input image signal; coding means for executing a coding process by using both the input image signal which is read out from one of the first and second frame memories and a reference signal which is read out from the other one of the first and second frame memories; decoding means for decoding a coded image signal from said coding means; signal path change means for allowing the first and second frame memories to alternately execute a first operation for reading out the stored input image signal and supplying said read out signal to said coding means and writing the decoded image signal which is generated from said decoding means, and for reading out the stored decoded image signal as a reference signal and supplying said decoded signal to said coding means and writing the input image signal in response to the frame change request which is generated from said coding means; and write limiting means, provided for each of the first and second frame memories, for stopping a subsequent writing operation of the frames written when a write address of the input image signal in said second operation approaches a read address of the reference signal and for restarting the writing operation from the head of the next frame.

Claim 12

An image coding apparatus according to claim 8, further comprising control means for delaying the output of said read address when said write address is compared with said read address and said comparison result is smaller than a predetermined value.

Claim 13

An image coding apparatus comprising: converting means for converting an input image signal to digital data; a frame memory for storing said digital data corresponding to one frame of said input signal, including: a write address generator for generating write addresses of said digital data to be written into the frame memory, a read address generator for generating read addresses of said digital data to be read out from the main memory, and means for outputting control signals to the read address generator by combining said write address with said read address; and coding means for coding said digital data read out from the frame memory in accordance with said read address.

Claim 14

An image coding apparatus comprising: converting means for converting an input image signal to digital data; a frame memory for storing said digital data corresponding to one frame of said input signal, including: a write address generator for generating write addresses of said digital data to be written into the frame memory, a read address generator for generating read addresses of said digital data to be read out from the main memory, and means for outputting control signals to the read address generator by combining said write address with said read address; and coding means for coding said digital data read out from the frame memory in accordance with said read address.