US4698676A
Expired / Lapsed
US
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Video signal control circuit
Assignee: Sony Corp
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Filing: 1986-04-11
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Granted: 1987-10-06
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Expires: 2006-04-11
Abstract
Abstract A video signal control circuit having a memory, a write address generator for generating a write address data supplied to the memory, by which an input digital video signal is written in the memory at the address represented by the write address data, a read address generator for generating a read address data supplied to the memory, by which a controlled digital video signal is read out from the memory at the address represented by the read address data, an address comparator for comparing the write and read address data and for generating a compared output pulse, a timing pulse generator for generating first and second timing pulses, each of which has a predetermined pulse duration, a still picture detector supplied with the input digital video signal and for detecting whether the input digital video signal represents a still picture or not, a write address controller supplied with the compared output pulse, the first timing pulse and the output of the still picture detector and for controlling the write address generator when the pulse duration of the compared output pulse is shorter than that of said first timing pulse and the still picture detector detects that the input digital video signal represents a still picture, and a read address controller supplied with the compared output pulse, the second timing pulse and the output of the still picture detector and for controlling the read address generator when the pulse duration of the compared output pulse is shorter than that of the second timing pulse and the still picture detector means detects that the input digital video signal represents a still picture.
Inventors
- 👤 Tatsuya Kubota
- 👤 Kenji Takanashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:49
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/01; H04N7/0135; H04N7/0137; H04N5/00; H04N5/04; H04N5/06; H04N5/067; H04N5/073; H04N5/0736; H04N7/0105
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
307 words
A video signal control circuit having a memory in which an input digital video signal is written and from which a controlled digital video signal is read out, and a memory control circuit, said video signal control circuit comprising: (A) write address generating means for generating a write address data supplied to said memory, and said input digital video signal being written in the address represented by said write address data; (B) read address generating means for generating a read address data supplied to said memory, and said controlled digital video signal being read out from the address represented by said read address data; (C) address comparator means for comparing said write and read address data and for generating a compared output pulse; (D) timing pulse generating means for generating first and second timing pulses, each of said timing pulses having a predetermined pulse duration; (E) still picture detecting means supplied with said input digital video signal and for detecting whether said input digital video signal represents a still picture or not; (F) write address control means supplied with said compared output pulse, said first timing pulse and the output of said still picture detecting means, and for controlling said write address generating means when the pulse duration of said compared output pulse is shorter than that of said first timing pulse and said still picture detecting means detects that said input digital video signal represents a still picture; and (G) read address control means supplied with said compared output pulse, said second timing pulse and the output of said still picture detecting means, and for controlling said read address generating means when the pulse duration of said compared output pulse is shorter than that of said second timing pulse and said still picture detecting means detects that said input digital video signal represents a still picture.
Claim 2
Dependent Claim
307 words
A video signal control circuit having a memory in which an input digital video signal is written and from which a controlled digital video signal is read out, and a memory control circuit, said video signal control circuit comprising: (A) write address generating means for generating a write address data supplied to said memory, and said input digital video signal being written in the address represented by said write address data; (B) read address generating means for generating a read address data supplied to said memory, and said controlled digital video signal being read out from the address represented by said read address data; (C) address comparator means for comparing said write and read address data and for generating a compared output pulse; (D) timing pulse generating means for generating first and second timing pulses, each of said timing pulses having a predetermined pulse duration; (E) still picture detecting means supplied with said input digital video signal and for detecting whether said input digital video signal represents a still picture or not; (F) write address control means supplied with said compared output pulse, said first timing pulse and the output of said still picture detecting means, and for controlling said write address generating means when the pulse duration of said compared output pulse is shorter than that of said first timing pulse and said still picture detecting means detects that said input digital video signal represents a still picture; and (G) read address control means supplied with said compared output pulse, said second timing pulse and the output of said still picture detecting means, and for controlling said read address generating means when the pulse duration of said compared output pulse is shorter than that of said second timing pulse and said still picture detecting means detects that said input digital video signal represents a still picture.
Claim 3
Dependent Claim
56 words
A video signal control circuit according to claim 1, wherein said write address generating means is controlled by a vertical synchronizing signal of said input digital video signal and said read address generating means is controlled by a reference signal, and said memory is capable of storing said input digital video signal of two frame periods.
Claim 4
Dependent Claim
61 words
A video signal control circuit according to claim 1, wherein said still picture detecting means includes a subtracter for subtracting a one frame delayed digital video signal from the input digital video signal, a comparator for comparing the output of said subtracter with a reference level, and a discriminator for discriminating the output of said comparator and for generating the output.
Claim 5
Dependent Claim
29 words
A video signal control circuit according to claim 1, wherein said address comparator means compares the pulses representing MSBs (most significant bits) of said write and read address data.
Claim 6
Dependent Claim
74 words
A video signal control circuit according to claim 4, wherein each of said write and read address control means includes a first AND gate supplied with the output of said address comparator means and a first or second timing pulse, a flip-flop circuit supplied with the output of said first AND gate, and a second AND gate supplied with the output of said flip-flop circuit and the output of said still picture detecting means.
Claim 7
Dependent Claim
84 words
A video signal control circuit according to claim 4, wherein each of said write and read address control means further includes a third AND gate supplied with the output of said address comparator means and a third or fourth timing pulse whose pulse duration is shorter than that of said first or second timing pulse, flip-flop means supplied with the output of said third AND gate means, and OR gate means supplied with the outputs of said second AND gate and said flip-flop means.
Claim 8
Dependent Claim
28 words
A video signal control circuit according to claim 1, wherein said timing pulse generating means is controlled by a vertical synchronizing signal of said input digital video signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-10-05 | 1991-04-06 | 1991-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-10-05 | 1995-04-06 | 1995-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-10-05 | 1999-04-06 | 1999-10-06 | $7700.00 | Window Closed / Lapsed |