Snubber circuit for a power semiconductor device

Claim 1

A snubber system, for suppressing voltage spikes applied to a switching circuit comprising: a power semiconductor device, having anode, cathode and control electrodes, which is subject to undesirable voltage spikes applied between said anode and cathode electrodes; snubber semiconductor means, comprising a bipolar transistor having anode and cathode electrodes respectively connected to the corresponding electrodes of said power semiconductor device, for providing a low inductance coupled junction capacitance responsive to the steeply rising leading edge of said voltage spikes for causing said snubber semiconductor means to rapidly turn on to suppress said voltage spikes; resistive means, connected between said cathode electrode and a control electrode of said snubber semiconductor means, for providing a junction capacitance resistive discharge path determinative of the turn-off time of said bipolar transistor; and a capacitor connected in parallel with said resistive means; whereby, improved suppression efficiency is provided by rapid turn-on in the absence of excess inductance and resistance controlled turn-off of the snubber semiconductor means.