Patent US5341480A successfully refreshed from Google Patents.
US5341480A
Expired / Lapsed
US
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Method and apparatus for providing a two conductor serial bus
Assignee: Apple Inc
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Filing: 1992-04-09
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Granted: 1994-08-23
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Expires: 2012-04-09
Abstract
Abstract A method for rapidly transferring serial data in a two conductor busing arrangement in which one conductor is utilized to transfer data and the other conductor is utilized to transfer clock signals, and in which a plurality of components are connected to the two conductors, at least one of which is capable of acting as a bus master including the steps of providing clock signals on the clock conductor which are active on both edges, placing a special signal on the data conductor to indicate the start of an operation, placing address data on the data conductor to indicate an address on the data conductor, placing data on the data conductor to indicate the type of transfer to be made, acknowledging the receipt of the address by a component being addressed, transferring data on the data conductor, placing a special signal on the data conductor to indicate the end of the data transfer, transferring a signal indicating a parity count, and placing another special signal on the data conductor to indicate the end of the operation.
Inventors
- 👤 Steven Wasserman
- 👤 Steven Roskowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:43
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/423
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
393 words
A method for rapidly transferring serial data in a two conductor busing arrangement in which one conductor is utilized to transfer data and the other conductor is utilized to transfer clock signals, and in which a plurality of components are connected to the two conductors, wherein said components include a first master circuit, a second master circuit, a first slave circuit, a second slave circuit, and a single clock signal generator, comprising the steps of providing continuously periodic clock signals, from said clock signal generator, on the clock conductor, wherein each one of the clock signals has an active rising edge and an active falling edge, placing a first special signal, from at least one of said master circuits, on the data conductor to indicate the start of an operation, attempting to place a first set of address data, from said first master circuit, on the data conductor, wherein said first set of address data specifies an address of said first slave circuit, attempting to place a second set of address data, from said second master circuit, on the data conductor, wherein said second set of address data specifies an address of said second slave circuit, comparing, in each of said first and second master circuits, said first set of address data with said second set of address data, and granting the first master circuit access to the data conductor if a predetermined relationship between said first set of address data and said second set of address data is satisfied, placing data, from said first master circuit, on the data conductor to indicate a transfer requiring one of said first master circuit and said first slave circuit to act as a transmitting circuit, and the other one of said first master circuit and said first slave circuit to act as a receiving circuit, placing an acknowledge signal, from said first slave circuit, on the data conductor after said first slave circuit verifies that said transmitted first set of address data matches the address of said first slave circuit, performing said transfer by said transmitting circuit sending data to said receiving circuit, placing a second special signal, from said transmitting circuit, on the data conductor to indicate the end of the transfer, and placing a third special signal, from said first master circuit, on the data conductor to indicate the end of the operation.
Claim 2
Independent Claim
393 words
A method for rapidly transferring serial data in a two conductor busing arrangement in which one conductor is utilized to transfer data and the other conductor is utilized to transfer clock signals, and in which a plurality of components are connected to the two conductors, wherein said components include a first master circuit, a second master circuit, a first slave circuit, a second slave circuit, and a single clock signal generator, comprising the steps of providing continuously periodic clock signals, from said clock signal generator, on the clock conductor, wherein each one of the clock signals has an active rising edge and an active falling edge, placing a first special signal, from at least one of said master circuits, on the data conductor to indicate the start of an operation, attempting to place a first set of address data, from said first master circuit, on the data conductor, wherein said first set of address data specifies an address of said first slave circuit, attempting to place a second set of address data, from said second master circuit, on the data conductor, wherein said second set of address data specifies an address of said second slave circuit, comparing, in each of said first and second master circuits, said first set of address data with said second set of address data, and granting the first master circuit access to the data conductor if a predetermined relationship between said first set of address data and said second set of address data is satisfied, placing data, from said first master circuit, on the data conductor to indicate a transfer requiring one of said first master circuit and said first slave circuit to act as a transmitting circuit, and the other one of said first master circuit and said first slave circuit to act as a receiving circuit, placing an acknowledge signal, from said first slave circuit, on the data conductor after said first slave circuit verifies that said transmitted first set of address data matches the address of said first slave circuit, performing said transfer by said transmitting circuit sending data to said receiving circuit, placing a second special signal, from said transmitting circuit, on the data conductor to indicate the end of the transfer, and placing a third special signal, from said first master circuit, on the data conductor to indicate the end of the operation.
Claim 3
Dependent Claim
83 words
A method for rapidly transferring serial data in a two conductor busing arrangement as claimed in claim 1 further comprising the steps of transferring, from said first slave circuit to said first master circuit, a signal indicating a parity count on the data conductor, comparing the parity count with a parity count retained by said first master circuit, and aborting said operation when the parity count transferred from said first slave circuit differs from said parity count retained by said first master circuit.
Claim 4
Dependent Claim
52 words
A method for rapidly transferring serial data in a two conductor busing arrangement as claimed in claim 2 wherein said address data are transferred most significant bit first, and wherein the first set of address data represents a lower numbered address than the address represented by the second set of address data.
Claim 5
Dependent Claim
238 words
A two conductor serial bus interface coupled to a single clock signal generator, wherein said two conductor serial bus interface provides a plurality of components with a means for communication and comprises a bus having a first conductor coupled to said components for transferring continuously periodic clock signals, wherein said clock signal generator produces said clock signals and supplies said clock signals to said first conductor, and wherein each one of said clock signals has an active rising edge and an active falling edge, and a second conductor coupled to said components for transferring data, addressing means coupled to said bus for initially attempting to place address bits on the second conductor most significant bit first, wherein said address bits specify the address of one of said components, comparison means coupled to said bus for comparing each address bit with the voltage level on the second conductor as said addressing means attempts to place each one of said address bits on the second conductor, terminating means coupled to said bus for aborting said addressing means' initial attempt to place said address bits on said second conductor when said addressing means attempts to place an address bit having a high voltage value on said bus and the voltage level on said second conductor is low, and announcing means coupled to said bus for indicating that said addressing means has successfully placed all said address bits on said second conductor.
Claim 6
Dependent Claim
238 words
A two conductor serial bus interface coupled to a single clock signal generator, wherein said two conductor serial bus interface provides a plurality of components with a means for communication and comprises a bus having a first conductor coupled to said components for transferring continuously periodic clock signals, wherein said clock signal generator produces said clock signals and supplies said clock signals to said first conductor, and wherein each one of said clock signals has an active rising edge and an active falling edge, and a second conductor coupled to said components for transferring data, addressing means coupled to said bus for initially attempting to place address bits on the second conductor most significant bit first, wherein said address bits specify the address of one of said components, comparison means coupled to said bus for comparing each address bit with the voltage level on the second conductor as said addressing means attempts to place each one of said address bits on the second conductor, terminating means coupled to said bus for aborting said addressing means' initial attempt to place said address bits on said second conductor when said addressing means attempts to place an address bit having a high voltage value on said bus and the voltage level on said second conductor is low, and announcing means coupled to said bus for indicating that said addressing means has successfully placed all said address bits on said second conductor.
Claim 7
Dependent Claim
50 words
A two conductor serial bus interface as claimed in claim 4 which further comprises means coupled to said bus for enabling said addressing means to re-try to place address bits on said second conductor after the terminating means aborts said initial attempt to place address bits on said second conductor.
Claim 8
Dependent Claim
36 words
A two conductor serial bus interface as claimed in claim 5 wherein said announcing means produces a completion signal, and wherein said bus interface further comprises means coupled to said bus for detecting the completion signal.
Claim 9
Dependent Claim
22 words
A two conductor serial bus interface as claimed in claim 4 in which the address of each component is programmable by software.
References Cited (Backward Citations)
US4195351A
Cited
US4689740A
Cited
US4847867A
Cited
US4899143A
Cited
US5063561A
Cited
US5119292A
Cited
US5175750A
Cited
US5195185A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |