Programmable input buffer

Claim 2

An input buffer capable of operating at a plurality of power supply levels in an integrated circuit, said input buffer comprising: input means for receiving a data input and generating a signal indicative of the data input, said input means having a means for determining the logic state of the data input, said means for determining having a pull-up means and pull-down means that create a trip point which is responsive to the power supply level, wherein the input means also includes a first MOS circuit coupled to the pull-up means, where said first MOS circuit increases the strength of the pull-up means when the input buffer operates at a first of the plurality of power supply levels, and wherein said input means further comprises a second MOS circuit coupled to the pull-down means, where the second MOS circuit increases the strength of the pull-down means when the input buffer operates at a second of the plurality of power supply levels, wherein the power supply levels are changed, the strength of the pull-up and the pull-down means is adjusted such that the trip point remains the same for all power supply levels; and output means coupled to said input means for outputting said data input in response to said signal.

Claim 3

The input buffer as defined in claim 1 further comprising enabling means for enabling the input buffer in response to an enable signal.

Claim 4

The input buffer as defined in claim 2 further comprising means to put the output in a predetermined state when disabled.

Claim 5

The input buffer as defined in claim 3 wherein said means to put the output in a predetermined state comprises a transistor.

Claim 6

The input buffer as defined in claim 1 wherein said output means outputs the data at one of the plurality of power supply levels.

Claim 7

An input buffer capable of operating at a plurality of power supply levels comprising: input means for receiving a data input, wherein said input means includes pull-up and pull-down means coupled in series and having a trip point, and further wherein the pull-up and pull-down means generates a signal indicative of the logic state of the data input; means for adjusting the pull-up and pull-down means according to the power supply level, such that the trip point remains the same for all power supply levels, wherein the means for adjusting includes a first MOS circuit coupled to the pull-up means, where said first MOS circuit increases the strength of the pull-up means when the input buffer operates at a first of the plurality of power supply levels, and wherein said input means further comprises a second MOS circuit coupled to the pull-down means, where the second MOS circuit increases the strength of the pull-down means when the input buffer operates at a second of the plurality of dower supply levels; and output means coupled to said input means for outputting said data input in response to said signal.

Claim 8

An input buffer capable of operating at a plurality of power supply levels comprising: input means for receiving a data input, wherein said input means includes pull-up and pull-down means coupled in series and having a trip point, and further wherein the pull-up and pull-down means generates a signal indicative of the logic state of the data input; means for adjusting the pull-up and pull-down means according to the power supply level, such that the trip point remains the same for all power supply levels, wherein the means for adjusting includes a first MOS circuit coupled to the pull-up means, where said first MOS circuit increases the strength of the pull-up means when the input buffer operates at a first of the plurality of power supply levels, and wherein said input means further comprises a second MOS circuit coupled to the pull-down means, where the second MOS circuit increases the strength of the pull-down means when the input buffer operates at a second of the plurality of dower supply levels; and output means coupled to said input means for outputting said data input in response to said signal.

Claim 9

The input buffer as defined in claim 6 wherein pull-up and pull-down means forms a first inverter.

Claim 10

The input buffer as defined in claim 7 wherein said output means comprises a second inverter.

Claim 11

The input buffer as defined in claim 6 wherein the input means and means for adjusting operate according to one of the plurality of power supply levels.

Claim 12

The input buffer as defined in claim 6 further comprising means coupled to the input means for compensating for fluctuations on the data input, wherein said means for compensating maintains the signal at a first logic state for a predetermined period of time based on the strength of the data input before generating the signal at a second logic state to ensure the data input has changed, such that the trip point is not tripped at the incorrect time.

Claim 13

The input buffer as defined in claim 10 wherein said means for compensating comprises a hysteresis device.

Claim 14

The input buffer as defined in claim 11 wherein the hysteresis device comprises a transistor device.

Claim 15

The input buffer as defined in claim 6 further comprising latching means for the latching the data input from the output means.

Claim 16

A processor for use in a computer system, said processor comprising: core logic, wherein the core logic processes data; a bus controller coupled to the core logic, wherein the bus controller controls communication between the core logic and a bus in the computer system; a memory control unit coupled to the core logic, wherein the memory control unit controls communication between the core logic and a memory in the computer system; wherein the bus controller includes a first plurality of input buffers, wherein at least one of the first plurality of input buffers includes: first input means for receiving a first data input, wherein said first input means includes a first pull-up and a first pull-down means coupled in series and having a trip point, and further wherein the first pull-up and first pull-down means generates a signal indicative of the logic state of the data input; first means for adjusting the first pull-up and first pull-down means according to the power supply level, such that the trip point remains the same for all power supply levels, wherein the first means for adjusting comprises two transistor means, one of the two transistor means for increasing the strength of the first pull-up means and the other of the two transistor means for increasing the strength of the first pull-down means; and first output means coupled to said first input means for outputting said first data input in response to said first signal.

Claim 17

A processor for use in a computer system, said processor comprising: core logic, wherein the core logic processes data; a bus controller coupled to the core logic, wherein the bus controller controls communication between the core logic and a bus in the computer system; a memory control unit coupled to the core logic, wherein the memory control unit controls communication between the core logic and a memory in the computer system; wherein the bus controller includes a first plurality of input buffers, wherein at least one of the first plurality of input buffers includes: first input means for receiving a first data input, wherein said first input means includes a first pull-up and a first pull-down means coupled in series and having a trip point, and further wherein the first pull-up and first pull-down means generates a signal indicative of the logic state of the data input; first means for adjusting the first pull-up and first pull-down means according to the power supply level, such that the trip point remains the same for all power supply levels, wherein the first means for adjusting comprises two transistor means, one of the two transistor means for increasing the strength of the first pull-up means and the other of the two transistor means for increasing the strength of the first pull-down means; and first output means coupled to said first input means for outputting said first data input in response to said first signal.

Claim 18

The processor defined in claim 14 wherein the memory control unit includes a second plurality of input buffers, wherein at least one of the second plurality of input buffers includes: second input means for receiving a second data input, wherein said second input means includes second pull-up and second pull-down means coupled in series and having a trip point, and further wherein the second pull-up and second pull-down means generates a second signal indicative of the logic state of the second data input; second means for adjusting the second pull-up and second pull-down means according to the power supply level, such that the trip point remains the same for all power supply levels, wherein the second means for adjusting comprises two transistor means, one of the two transistor means for increasing the strength of the second pull-up means and the other of the two transistor means for increasing the strength of the second pull-down means; and second output means coupled to said second input means for outputting said second data input in response to said second signal.

Claim 19

The processor defined in claim 14 further comprising means to put the output in a predetermined state when disabled.

Claim 20

The processor defined in claim 14 wherein said output means outputs the data at one of the plurality of power supply levels.

Claim 21

The processor defined in claim 14 wherein said input means and means for adjusting operate according to one of the plurality of power supply levels.

Claim 22

The processor defined in claim 14 further comprising means coupled to the input means for compensating for fluctuations on the data input, wherein said means for compensating maintains the signal at a first logic state for a predetermined period of time based on the strength of the data input before generating the signal at a second logic state to ensure the data input has changed such that the trip point is not tripped at the incorrect time.