Patent US5341003A successfully refreshed from Google Patents.
US5341003A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS semiconductor device having a main unit element and a sense unit element for monitoring the current in the main unit element
Assignee: Fuji Electric Co Ltd
•
Filing: 1992-06-09
•
Granted: 1994-08-23
•
Expires: 2012-06-09
Abstract
Abstract A MOS semiconductor device is disclosed for monitoring the value of the current flowing through an element by outputting a sense signal. The semiconductor has a main unit element and a sense unit element formed in a semiconductor layer, and the current flowing through the sense unit element is proportional to the current flowing through the main unit element. Both the main unit element and the sense unit element have a base region, a source region, a gate electrode, and a source electrode. A doped region of the same conductivity type as the base regions is formed in the semiconductor layer between the base regions of the main unit element and the sense unit element. This doped region is in contact with the source electrode of the main unit element. This structure decreases the power loss due to the sense signal current and ensures a linear relationship between the sense signal current and the main current.
Inventors
- 👤 Shigeyuki Obinata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/669; H10D12/00; H10D12/411; H10D12/441; H10D62/00; H10D62/10; H10D62/17; H10D62/393
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
215 words
A MOS semiconductor device comprising: a semiconductor layer of a first conductivity type; a plurality of first regions having a second conductivity type formed in a surface region of said semiconductor layer; a plurality of second regions of said first conductivity type formed in a surface region of said first region; channel forming regions located in said first regions between said second regions and said semiconductor layer; a gate electrode formed on a gate insulating film which is formed on each of said channel forming regions; a main source electrode which contacts a first one of said plurality of first regions and a first one of said plurality of second regions; a sense signal pickup source electrode which contacts a second one of said plurality of first regions and a second one of said plurality of second regions; resistor means for providing a resistance connected between said main source electrode and said sense signal pickup source electrode; and a third region of said second conductivity type formed in a surface region of said semiconductor layer located between said first one of said plurality of first regions and said second one of said plurality of first regions, said third region being located apart from said first regions, and being in contact with said main source electrode.
Claim 2
Dependent Claim
215 words
A MOS semiconductor device comprising: a semiconductor layer of a first conductivity type; a plurality of first regions having a second conductivity type formed in a surface region of said semiconductor layer; a plurality of second regions of said first conductivity type formed in a surface region of said first region; channel forming regions located in said first regions between said second regions and said semiconductor layer; a gate electrode formed on a gate insulating film which is formed on each of said channel forming regions; a main source electrode which contacts a first one of said plurality of first regions and a first one of said plurality of second regions; a sense signal pickup source electrode which contacts a second one of said plurality of first regions and a second one of said plurality of second regions; resistor means for providing a resistance connected between said main source electrode and said sense signal pickup source electrode; and a third region of said second conductivity type formed in a surface region of said semiconductor layer located between said first one of said plurality of first regions and said second one of said plurality of first regions, said third region being located apart from said first regions, and being in contact with said main source electrode.
Claim 3
Dependent Claim
45 words
A MOS semiconductor device according to claim 1, wherein a fourth region of said first conductivity type having a high impurity concentration is formed adjacent to a surface of said semiconductor layer which is opposite to the surface in which said first regions are formed.
Claim 4
Dependent Claim
45 words
A MOS semiconductor device according to claim 1, wherein a fifth region of said second conductivity type having a high impurity concentration is formed adjacent to a surface of said semiconductor layer which is opposite to the surface in which said first regions are formed.
Claim 5
Dependent Claim
19 words
A MOS semiconductor device according to claim 1, further comprising a common drain electrode connected to said semiconductor layer.
Claim 6
Dependent Claim
28 words
A MOS semiconductor device according to claim 1, wherein said gate electrode formed on said gate insulating film extends over at least a part of said third region.
Claim 7
Dependent Claim
75 words
A MOS semiconductor device according to claim 1, wherein a first depletion layer is formed at a junction of said first region and said semiconductor layer in response to the application of power to said gate electrode, and a second depletion layer is formed at a junction of said third region and said semiconductor layer in response to the application of power to said gate electrode, said first and second depletion layers being similarly expandable.
Claim 8
Dependent Claim
22 words
A MOS semiconductor device according to claim 1, wherein said first regions are base regions and said second regions are source regions.
Claim 9
Dependent Claim
171 words
A MOS semiconductor device comprising: a semiconductor layer having impurities of a first conductivity type; a main unit element formed in said semiconductor layer including a base layer, a source layer, a gate electrode, and a main source electrode contacting said base layer and said source layer of said main unit element; a sense unit element formed in said semiconductor layer including a base layer, a source layer, a gate electrode, and a sense signal pickup source electrode contacting said base layer and said source layer of said sense unit element; resistor means for providing a resistance between said main source electrode and said sense signal pickup source electrode; and a doped region formed in a surface of said semiconductor layer between the base layer of said main unit element and the base layer of said sense unit element, said doped region formed apart from said base layer of said main unit element and said base layer of said sense unit element and being in contact with said main source electrode.
Claim 10
Dependent Claim
171 words
A MOS semiconductor device comprising: a semiconductor layer having impurities of a first conductivity type; a main unit element formed in said semiconductor layer including a base layer, a source layer, a gate electrode, and a main source electrode contacting said base layer and said source layer of said main unit element; a sense unit element formed in said semiconductor layer including a base layer, a source layer, a gate electrode, and a sense signal pickup source electrode contacting said base layer and said source layer of said sense unit element; resistor means for providing a resistance between said main source electrode and said sense signal pickup source electrode; and a doped region formed in a surface of said semiconductor layer between the base layer of said main unit element and the base layer of said sense unit element, said doped region formed apart from said base layer of said main unit element and said base layer of said sense unit element and being in contact with said main source electrode.
Claim 11
Dependent Claim
62 words
A MOS semiconductor device according to claim 8, further comprising a buffer layer having impurities of said first conductivity type and having a high impurity concentration formed adjacent to a surface of said semiconductor layer which is opposite to the surface in which the base layer of said main element unit and the base layer of said sense unit element are formed.
Claim 12
Dependent Claim
56 words
A MOS semiconductor device according to claim 8, further comprising a drain layer having impurities of a second conductivity type formed adjacent to a surface of said semiconductor layer which is opposite to the surface in which the base layer of said main element unit and the base layer of said sense unit element are formed.
Claim 13
Dependent Claim
73 words
A MOS semiconductor device according to claim 8, further comprising a first channel forming region located in the base layer of said main unit element in a region between said source layer of said main unit element and the semiconductor layer, and a second channel forming region located in the base layer of said sense unit element in a region between said source layer of said sense unit element and the semiconductor layer.
Claim 14
Dependent Claim
25 words
A MOS semiconductor device according to claim 8, further comprising a common drain electrode connected to said main unit element and said sense unit element.
Claim 15
Dependent Claim
23 words
A MOS semiconductor device according to claim 8, wherein said main unit element and said sense unit element have a common gate terminal.
Claim 16
Dependent Claim
34 words
A MOS semiconductor device according to claim 8, wherein said doped region, said base layer of said main unit element, and said base layer of said sense unit element have the same conductivity type.
Claim 17
Dependent Claim
27 words
A MOS semiconductor device according to claim 8, wherein said gate electrode of said sense unit element extends over at least a part of said doped region.
Claim 18
Dependent Claim
80 words
A MOS semiconductor device according to claim 8, wherein a first depletion layer is formed at a junction of said base layer of said sense unit element and said semiconductor layer in response to the application of power to said gate electrode, and a second depletion layer is formed at a junction of said doped region and said semiconductor layer in response to the application of power to said gate electrode, said first and second depletion layers being similarly expandable.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |