US5339426A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for resume processing initialization
Assignee: Toshiba America Information Systems Inc
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Filing: 1993-12-07
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Granted: 1994-08-16
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Expires: 2013-12-07
Abstract
Abstract A resume processing driver for an advanced operating system, such as OS/2, is provided which saves data indicative of the operating conditions of the advanced operating system into system memory and then calls a previously existing resume processing routine designed for a previously existing operating system, such as MS-DOS. The previously existing resume processing routine performs additional processing in order to save operating condition data associated with the previously existing operating system into system memory, and then performs a controlled power off sequence and removes the power supplied to all elements of the computer except the computer memory. Thereafter, the existing resume processing routine performs processing to restore the operating condition data associated with the previously existing operating system from system memory and then passes control to the resume processing driver of the present invention. The resume processing driver restores the data indicative of the operating conditions of the advanced operating system from system memory, and control then passes to the computer program which was executing before the resume processing driver was initiated.
Inventors
- 👤 Kinya Aoshima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:07
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4418; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F2200/00; G06F2200/16; G06F2200/161; G06F2200/1613
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
84 words
An apparatus for setting a periodic interrupt rate of a real time clock in a computer system, having an operating system, comprising; a power-up signal detector for indicating that computer system information is to be reset; an enabler, responsive to said power-up signal detector, for enabling an A20 address line; and a clock setter, responsive to said power-up signal detector, for configuring the real time clock such that the periodic interrupt rate is set to a specified periodic interrupt rate for the operating system.
Claim 2
Independent Claim
84 words
An apparatus for setting a periodic interrupt rate of a real time clock in a computer system, having an operating system, comprising; a power-up signal detector for indicating that computer system information is to be reset; an enabler, responsive to said power-up signal detector, for enabling an A20 address line; and a clock setter, responsive to said power-up signal detector, for configuring the real time clock such that the periodic interrupt rate is set to a specified periodic interrupt rate for the operating system.
Claim 3
Dependent Claim
12 words
The apparatus of claim 1, wherein said enabler is a keyboard controller.
Claim 4
Independent Claim
121 words
An apparatus for use in a computer system having 1) a CPU capable of operating in a real mode and a protected mode, 2) an adjustable real time clock having a periodic interrupt rate, and 3) an operating system using a specified periodic interrupt rate and capable of operating in the real mode and the protected mode, said apparatus capable of resetting information indicative of a prior state of the computer system, comprising: power-up signal detection means for indicating that computer system information is to be reset; and configuration means, responsive to said power-up signal detection means, for configuring the real time clock such that the periodic interrupt rate is reset to the specified periodic interrupt rate for the operating system.
Claim 5
Independent Claim
121 words
An apparatus for use in a computer system having 1) a CPU capable of operating in a real mode and a protected mode, 2) an adjustable real time clock having a periodic interrupt rate, and 3) an operating system using a specified periodic interrupt rate and capable of operating in the real mode and the protected mode, said apparatus capable of resetting information indicative of a prior state of the computer system, comprising: power-up signal detection means for indicating that computer system information is to be reset; and configuration means, responsive to said power-up signal detection means, for configuring the real time clock such that the periodic interrupt rate is reset to the specified periodic interrupt rate for the operating system.
Claim 6
Dependent Claim
22 words
The apparatus of claim 3, further comprising enabling means, responsive to said power-up signal detection means, for enabling an A20 address line.
Claim 7
Dependent Claim
19 words
The apparatus of claim 4, wherein said enabling means utilizes a keyboard controller to enable said A20 address line.
Claim 8
Dependent Claim
26 words
The apparatus of claim 3, wherein said configuration means sets the periodic interrupt rate of the real time clock to correspond to the OS/2 operating system.
Claim 9
Dependent Claim
101 words
A computer system capable of resetting itself to a prior state, comprising: CPU means capable of operating in a real mode and a protected mode; real time clock means having a periodic interrupt rate; operating system means capable of operating in connection with said CPU means, said operating system means using a specified periodic interrupt rate; power-up signal detection means for indicating that the prior state is to be reinstated; configuration means, responsive to said enabling means, for configuring the real time clock such that the periodic interrupt rate is set to the specified periodic interrupt rate for the operating system.
Claim 10
Dependent Claim
101 words
A computer system capable of resetting itself to a prior state, comprising: CPU means capable of operating in a real mode and a protected mode; real time clock means having a periodic interrupt rate; operating system means capable of operating in connection with said CPU means, said operating system means using a specified periodic interrupt rate; power-up signal detection means for indicating that the prior state is to be reinstated; configuration means, responsive to said enabling means, for configuring the real time clock such that the periodic interrupt rate is set to the specified periodic interrupt rate for the operating system.
Claim 11
Dependent Claim
23 words
The computer system of claim 7, further comprising enabling means, responsive to said power-up signal detector means, for enabling an A20 address line.
Claim 12
Independent Claim
92 words
A method for resetting and configuring a real time clock in a computer system having 1) a CPU capable of operating in a real mode and a protected mode, 2) an adjustable real time clock having a periodic interrupt rate, and 3) an operating system using a specified periodic interrupt rate, comprising the steps of: (1) receiving an indication that computer system information is to be reset; and (2) configuring the real time clock such that the periodic interrupt rate is reset to the specified periodic interrupt rate for the operating system.
Claim 13
Independent Claim
92 words
A method for resetting and configuring a real time clock in a computer system having 1) a CPU capable of operating in a real mode and a protected mode, 2) an adjustable real time clock having a periodic interrupt rate, and 3) an operating system using a specified periodic interrupt rate, comprising the steps of: (1) receiving an indication that computer system information is to be reset; and (2) configuring the real time clock such that the periodic interrupt rate is reset to the specified periodic interrupt rate for the operating system.
Claim 14
Dependent Claim
21 words
The method of claim 9, further comprising the step of enabling an A20 address line in response to said step (1).
Claim 15
Dependent Claim
23 words
The method of claim 10, wherein said step (2) comprises the step of utilizing a keyboard controller to enable said A20 address line.
Claim 16
Dependent Claim
73 words
The method of claim 11, wherein said step of utilizing a keyboard controller comprises the steps of: (3) waiting for a keyboard controller input buffer of said keyboard controller to become empty; (4) requesting to write to an output port; (5) sending a byte with bit 1 set to said output port; and (6) sending a null pulse output port command to the keyboard controller after said A20 address line has been enabled.
References Cited (Backward Citations)
US4432049A
Cited
US4779187A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |