Block erasable flash EEPROM apparatus and method thereof

Claim 2

An electrically erasable programmable read only memory (EEPROM), comprising: a plurality of bit lines; an array of flash EEPROM memory cells, said array of flash EEPROM memory cells having a first block of flash EEPROM memory cells and a second block of flash EEPROM memory cells, the first block of flash EEPROM memory cells being coupled to the second block of flash EEPROM memory cells by way of said plurality of bit lines; a first charge pump circuit; and a second charge pump circuit; wherein the first block of flash EEPROM memory cells comprises: at least a portion of a first row; a first source conductor coupled to said at least the portion of the first row; and a first block conductor coupled to said first source conductor and to said first charge pump circuit; and wherein the second block of flash EEPROM memory cells comprises: at least a portion of a second row; a second source conductor coupled to said at least the portion of the second row; and a second block conductor coupled to said second source conductor and to said second charge pump circuit; and wherein said first block of flash EEPROM memory cells can be erased independently of said second block of flash EEPROM memory cells.

Claim 3

An electrically erasable programmable read only memory (EEPROM) as in claim 1, wherein said first charge pump comprises: a first capacitor having a first predetermined capacitance value; and wherein said second charge pump comprises: a second capacitor having a second predetermined capacitance value.

Claim 4

An electrically erasable programmable read only memory (EEPROM) as in claim 2, wherein said first and second predetermined capacitance values are selectively determined during manufacture of the electrically erasable programmable read only memory (EEPROM).

Claim 5

An electrically erasable programmable read only memory (EEPROM) as in claim 1, wherein the first block of flash EEPROM memory cells further comprises: a first via for coupling said first block conductor to said first source conductor; and wherein the second block of flash EEPROM memory cells further comprises: a second via for coupling said second block conductor to said second source conductor.

Claim 6

An electrically erasable programmable read only memory (EEPROM) as in claim 1, wherein the first block of flash EEPROM memory cells further comprises: a third row; and a third source conductor coupled to said third row and coupled to said first block conductor; and wherein the second block of flash EEPROM memory cells further comprises: a fourth row; and a fourth source conductor coupled to said fourth row and coupled to said second block conductor.

Claim 7

An electrically erasable programmable read only memory (EEPROM) as in claim 1, further comprising: decode circuitry, coupled to said array of flash EEPROM memory cells, said decode circuitry asserting a first block select signal to select the first block of flash EEPROM memory cells during a first erase procedure, said decode circuitry asserting a second block select signal to select the second block of flash EEPROM memory cells during a second erase procedure.

Claim 8

An electrically erasable programmable read only memory (EEPROM) as in claim 6, wherein said decode circuitry provides a plurality of column select signals.

Claim 9

An electrically erasable programmable read only memory (EEPROM) as in claim 7, further comprising: row decode circuitry coupled to said array of flash EEPROM memory cells.

Claim 10

An electrically erasable programmable read only memory (EEPROM) as in claim 8, wherein said first charge pump circuit places a predetermined voltage level on said first block conductor during the first erase procedure, and wherein said second charge pump circuit places the predetermined voltage level on said second block conductor during the second erase procedure.

Claim 11

An electrically erasable programmable read only memory (EEPROM) as in claim 1, wherein the electrically erasable programmable read only memory (EEPROM) and a processing unit are located on a same integrated circuit.

Claim 12

A block erasable flash EEPROM memory, comprising: a decode circuit for receiving address signals and for providing a first block select signal and a second block select signal; a plurality of bit lines; an array of flash EEPROM memory cells coupled to said decode circuit, said array of flash EEPROM memory cells having a first block of flash EEPROM memory cells and a second block of flash EEPROM memory cells, the first block of flash EEPROM memory cells being coupled to the second block of flash EEPROM memory cells by way of said plurality of bit lines; and a plurality of charge pump circuits coupled to said decode circuit; wherein the first block of flash EEPROM memory cells comprises: a first plurality of rows; a first plurality of source conductors, each of said first plurality of source conductors being coupled to at least one row of the first plurality of rows; and a first block conductor coupled to all of said first plurality of source conductors and coupled to a first one of said plurality of charge pump circuits; and wherein the second block of flash EEPROM memory cells comprises: a second plurality of rows; a second plurality of source conductors, each of said second plurality of source conductors being coupled to at least one row of the second plurality of rows; and a second block conductor coupled to all of said second plurality of source conductors and coupled to a second one of said plurality of charge pump circuits; and wherein said first block of flash EEPROM memory cells can be erased independently of said second block of flash EEPROM memory cells.

Claim 13

A block erasable flash EEPROM memory, comprising: a decode circuit for receiving address signals and for providing a first block select signal and a second block select signal; a plurality of bit lines; an array of flash EEPROM memory cells coupled to said decode circuit, said array of flash EEPROM memory cells having a first block of flash EEPROM memory cells and a second block of flash EEPROM memory cells, the first block of flash EEPROM memory cells being coupled to the second block of flash EEPROM memory cells by way of said plurality of bit lines; and a plurality of charge pump circuits coupled to said decode circuit; wherein the first block of flash EEPROM memory cells comprises: a first plurality of rows; a first plurality of source conductors, each of said first plurality of source conductors being coupled to at least one row of the first plurality of rows; and a first block conductor coupled to all of said first plurality of source conductors and coupled to a first one of said plurality of charge pump circuits; and wherein the second block of flash EEPROM memory cells comprises: a second plurality of rows; a second plurality of source conductors, each of said second plurality of source conductors being coupled to at least one row of the second plurality of rows; and a second block conductor coupled to all of said second plurality of source conductors and coupled to a second one of said plurality of charge pump circuits; and wherein said first block of flash EEPROM memory cells can be erased independently of said second block of flash EEPROM memory cells.

Claim 14

A block erasable flash EEPROM memory as in claim 11, wherein each of the plurality of charge pump circuits comprises: a capacitor having a capacitance value; and wherein the capacitance value of each capacitor is determined by way of a mask option during manufacture of the block erasable flash EEPROM memory.

Claim 15

A block erasable flash EEPROM memory as in claim 12, wherein the first plurality of rows is a first positive whole number which is determined by way of the mask option during manufacture of the block erasable flash EEPROM memory, and wherein the second plurality of rows is a second positive whole number which is determined by way of the mask option during manufacture of the block erasable flash EEPROM memory.

Claim 18

A method for operating a block erasable flash EEPROM memory as in claim 14, further comprising the step of: determining if an erase initiation sequence has been completed.

Claim 19

A method for operating a block erasable flash EEPROM memory as in claim 14, further comprising the step of: selecting the first number of rows and the second number of rows as a mask option during manufacture of the block erasable flash EEPROM memory.

Claim 20

A method for operating a block erasable flash EEPROM memory as in claim 14, wherein the first erase voltage driver circuit is a first charge pump circuit, and the second erase voltage driver circuit is a second charge pump circuit.

Claim 21

A method for operating a block erasable flash EEPROM memory as in claim 17, wherein the electrical parameter is a capacitance parameter.

Claim 22

A method for operating a block erasable flash EEPROM memory as in claim 18, further comprising the step of: selecting the first value and the second value as a mask option during manufacture of the block erasable flash EEPROM memory.

Claim 23

A method for operating a block erasable flash EEPROM memory as in claim 19, further comprising the step of: selecting the first number of rows and the second number of rows by way of said mask option.