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US5338954A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor memory device having an insulating film and a trap film joined in a channel region

Assignee: Rohm Co Ltd
•
Filing: 1993-02-03
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Granted: 1994-08-16
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Expires: 2013-02-03
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Abstract

Abstract A semiconductor memory device and a method for producing the same are provided, wherein memory cells, in each of which a MONOS- or MNOS-type memory transistor is combined with an enhancement transistor in a reduced cell area, are arranged in a matrix configuration. With such a device and a method, an extremely high integration of memory cells can be realized with a reduced production cost. The semiconductor memory device of the present invention includes a gate insulating film and a trap film which are joinedly formed on a channel region of a semiconductor substrate of a first conductive type. A gate electrode extends over the two films. Source/drain regions are formed on opposite sides of the gate electrode

Inventors

  • 👤 Noriyuki Shimoji

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 15:33
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/683; H10D30/00; H10D30/01; H10D30/021; H10D30/0413; H10D30/60; H10D30/69; H10D64/685; H10D64/693

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 103 words
A semiconductor memory device having a plurality of memory transistors arranged in a matrix configuration, each of the memory transistors comprising a semiconductor substrate having a source region, a drain region and a channel region intermediate between the source and drain regions; a gate insulating film formed on one side of the channel region; a trap film formed on the other side of the channel region so as to join with the gate insulating film, said trap film comprises an insulating material; and a gate electrode formed only in the channel region and extending over the gate insulating film and the trap film.
Claim 2
Dependent Claim 103 words
A semiconductor memory device having a plurality of memory transistors arranged in a matrix configuration, each of the memory transistors comprising a semiconductor substrate having a source region, a drain region and a channel region intermediate between the source and drain regions; a gate insulating film formed on one side of the channel region; a trap film formed on the other side of the channel region so as to join with the gate insulating film, said trap film comprises an insulating material; and a gate electrode formed only in the channel region and extending over the gate insulating film and the trap film.
Claim 3
Dependent Claim 43 words
The semiconductor memory device as set forth in claim 1, wherein said trap film has of a three-layered structure including a silicon oxide film, a silicon nitride film and a silicon oxide film which are stacked in this order on said semiconductor substrate.
Claim 4
Dependent Claim 39 words
The semiconductor memory device as set forth in claim 1, wherein said trap film is of a double-layered structure having a silicon oxide film and a silicon nitride film which are stacked in this order on said semiconductor substrate.
Claim 5
Dependent Claim 25 words
The semiconductor memory device at set forth in claim 1, wherein said gate insulating film and said trap film are substantially coplanar with each other.
Claim 6
Dependent Claim 25 words
The semiconductor memory device as set forth in claim 1, wherein said trap film extends beyond said gate electrode onto the source or drain region.
Claim 7
Dependent Claim 21 words
The semiconductor memory device as set forth in claim 1, wherein said trap film is formed just under said gate electrode.
Claim 8
Dependent Claim 22 words
The semiconductor memory device as set forth in claim 1, wherein said gate electrode has a width of 0.4 to 1.0 μm.

References Cited (Backward Citations)

JPS5821871A Cited
US4616340A Cited
JPS58194369A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-15 1998-02-14 1998-08-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-15 2002-02-14 2002-08-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-15 2006-02-14 2006-08-16 $7700.00 Window Closed / Lapsed

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