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US5338750A Expired / Lapsed US ⏱️ 0.0 years remaining

Fabrication method to produce pit-free polysilicon buffer local oxidation isolation

Assignee: Industrial Technology Research Institute
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Filing: 1992-11-27
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Granted: 1994-08-16
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Expires: 2012-11-27
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Abstract

Abstract A method of forming a silicon oxide isolation region on the surface of a silicon wafer consisting of a thin layer of silicon oxide on the wafer, a layer of impurity-doped polysilicon, and a layer of silicon nitride. The oxidation mask is formed by patterning the silicon nitride layer and at least a portion of the doped polysilicon layer. The silicon oxide field isolation region is formed by subjecting the structure to a thermal oxidation ambient. The oxidation mask is removed in one continuous etching step using a single etchant, such as phosphoric acid which etches the silicon nitride and polysilicon layers at substantially the same rate to complete the formation of the isolation region without pitting the monocrystalline substrate.

Inventors

  • 👤 Hsiao-Chin Tuan
  • 👤 Hu H. Chao

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 03:02
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/61

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 163 words
A method of forming a silicon oxide isolation region on the surface of a silicon wafer comprising: forming a thin layer of silicon oxide on said wafer; forming a layer of undoped polysilicon on said silicon oxide layer; forming a layer of silicon nitride on said polysilicon layer; ion implanting an impurity into said layer of undoped polysilicon in a concentration greater than about 5 E 15 atoms/cm 3 to form a doped polysilicon layer, and not annealing the doped polysilicon; patterning said silicon nitride layer; forming said silicon oxide isolation region by thermal oxidation; and removing in one continuous etching step, using phosphoric acid (H 3 PO 4 ) at a temperature of between about 150° and 180° C., said silicon nitride and doped polysilicon layers to complete the formation of said isolation region on the surface of 15 said wafer, wherein the etching rate of said silicon nitride and doped polysilicon are closer because of said not annealing the doped polysilicon.
Claim 2
Independent Claim 163 words
A method of forming a silicon oxide isolation region on the surface of a silicon wafer comprising: forming a thin layer of silicon oxide on said wafer; forming a layer of undoped polysilicon on said silicon oxide layer; forming a layer of silicon nitride on said polysilicon layer; ion implanting an impurity into said layer of undoped polysilicon in a concentration greater than about 5 E 15 atoms/cm 3 to form a doped polysilicon layer, and not annealing the doped polysilicon; patterning said silicon nitride layer; forming said silicon oxide isolation region by thermal oxidation; and removing in one continuous etching step, using phosphoric acid (H 3 PO 4 ) at a temperature of between about 150° and 180° C., said silicon nitride and doped polysilicon layers to complete the formation of said isolation region on the surface of 15 said wafer, wherein the etching rate of said silicon nitride and doped polysilicon are closer because of said not annealing the doped polysilicon.
Claim 3
Dependent Claim 28 words
The method of claim 1 in which, during patterning of said silicon nitride layer, a portion of said polysilicon thickness is etched into, leaving a thickness of polysilicon.
Claim 4
Dependent Claim 19 words
The method of claim 1 wherein said phosphoric acid is comprised of a solution of water and phosphoric acid.
Claim 5
Dependent Claim 190 words
In the manufacture of very large scale integrated circuit device, a method for forming an isolation region on a portion of a planar silicon surface comprising: forming an oxidation mask structure on a silicon oxide layer, said structure consisting of a layer of doped polysilicon, said doped polysilicon having been doped by ion implanting into undoped polysilicon with an impurity with a concentration greater than about 5 E 15 atoms/cm 3 to form a doped polysilicon layer, and without annealing the doped polysilicon, over said silicon oxide and a layer of silicon nitride over said doped polysilicon layer; said mask structure covers the surface regions that are intended to be isolated from other such surface regions; forming said isolation region by oxidation of said portion of said planer silicon surface; and removing said oxidation mask structure by etching with phosphoric acid (H 3 PO 4 ) at a temperature of between about 150° and 180° C., that selectively etches silicon nitride and doped polysilicon at substantially the same rate, wherein the etching rate of said silicon nitride and doped polysilicon are closer because of said not annealing the doped polysilicon.
Claim 6
Dependent Claim 190 words
In the manufacture of very large scale integrated circuit device, a method for forming an isolation region on a portion of a planar silicon surface comprising: forming an oxidation mask structure on a silicon oxide layer, said structure consisting of a layer of doped polysilicon, said doped polysilicon having been doped by ion implanting into undoped polysilicon with an impurity with a concentration greater than about 5 E 15 atoms/cm 3 to form a doped polysilicon layer, and without annealing the doped polysilicon, over said silicon oxide and a layer of silicon nitride over said doped polysilicon layer; said mask structure covers the surface regions that are intended to be isolated from other such surface regions; forming said isolation region by oxidation of said portion of said planer silicon surface; and removing said oxidation mask structure by etching with phosphoric acid (H 3 PO 4 ) at a temperature of between about 150° and 180° C., that selectively etches silicon nitride and doped polysilicon at substantially the same rate, wherein the etching rate of said silicon nitride and doped polysilicon are closer because of said not annealing the doped polysilicon.
Claim 7
Dependent Claim 42 words
The method of claim 4 in which, said doped polysilicon layer is also present on the unmasked portions of said silicon oxide layer, wherein said thickness is less than the doped polysilicon layer which is a part of said oxidation mask structure.
Claim 8
Dependent Claim 48 words
The method of claim 5 wherein said thickness of said doped polysilicon layer in said mask structure is between about 1200 to 4000 Angstroms and the thickness of said doped polysilicon layer not part of said mask structure has a thickness of between about 1000 to 3500 Angstroms.
Claim 9
Dependent Claim 19 words
The method of claim 6 wherein said phosphoric acid is comprised of a solution of water and phosphoric acid.
Claim 10
Dependent Claim 30 words
The method of claim 4 wherein said polysilicon is doped with an phosphorus impurity greater than about 1 E 19 atoms/cm 3 which have been ion implanted into undoped polysilicon.
Claim 11
Dependent Claim 31 words
The method of claim 4 wherein said polysilicon is doped with an arsenic impurity greater than about 1 E 19 atoms/cm 3 which have been ion implanted into undoped 10 polysilicon.
Claim 12
Dependent Claim 30 words
The method of claim 4 wherein said polysilicon is doped with an boron impurity greater than about 1 E 19 atoms/cm 3 which have been ion implanted into undoped polysilicon.
Claim 13
Dependent Claim 23 words
The method of claim 1 wherein said undoped polysilicon is doped with an impurity greater than about 1 E 19 atoms/cm 3 .

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