Patent US5337415A successfully refreshed from Google Patents.
US5337415A
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Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency
Assignee: HP Inc
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Filing: 1992-12-04
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Granted: 1994-08-09
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Expires: 2012-12-04
Abstract
Abstract A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilization by a superscalar processor. The circuitry of the predecode unit is comprised of logic and latches. The predecode unit includes two main paths for transporting instruction information: a predecode path and an instruction path. The instruction path buffers instructions sent from memory to cache as information from these instructions are decoded in the predecode path. The predecode path includes a decoder and a bit information unit. The decoder identifies the instruction type by monitoring the op-code of instructions entering the predecode unit. The bit information unit is coupled to the decoder and receives signals indicating instruction type and passes these signals through logic gates to obtain whether instructions can be bundled. The bit information unit then transfers to cache bundle signals and instruction type signals. These signals are stored as predecode bits along with instructions from the instruction path in the cache.
Inventors
- 👤 Eric R. DeLano
- 👤 Craig A. Gleason
- 👤 Mark A. Forsyth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/382; G06F9/3802; G06F9/3822; G06F9/3836; G06F9/3853
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
270 words
A predecoder unit, which operates in a superscalar processor environment, for predecoding instructions for superscalar dependency information, said predecoder generates predecode bits from said instructions when said instructions are copied into a cache memory unit from a memory unit for utilization by a superscalar processor, the predecoder unit comprising: decoder means, coupled to the memory unit, for receiving encoded information from a first instruction and a second instruction, wherein said decoder means generates three bits in a first clock cycle indicative of whether said first instruction is a floating-point operation, a system operation, a branch operation or an integer operation, and generates three bits in a second clock cycle indicative of whether said second instruction is a floating-point operation, a system operation a branch operation or an integer operation; a first set of latches, coupled to said decoder means for storing during said first clock cycle said three bits from said first instruction and for storing during said second clock cycle said three bits from said second instruction; a second set of latches, coupled to said first set of latches, for storing during said second clock cycle said three bits from said first instruction; logic means, coupled to said first and second set of latches, for generating an active bundle signal, wherein said active bundle signal indicates that said first and second instructions will be executed simultaneously when: (a) said first and second instructions are integer instructions, (b) said first instruction is a floating-point operation and said second instruction is an integer instruction, or (c) said first instruction is floating point operation and said second instruction is a branch instruction.
Claim 2
Dependent Claim
270 words
A predecoder unit, which operates in a superscalar processor environment, for predecoding instructions for superscalar dependency information, said predecoder generates predecode bits from said instructions when said instructions are copied into a cache memory unit from a memory unit for utilization by a superscalar processor, the predecoder unit comprising: decoder means, coupled to the memory unit, for receiving encoded information from a first instruction and a second instruction, wherein said decoder means generates three bits in a first clock cycle indicative of whether said first instruction is a floating-point operation, a system operation, a branch operation or an integer operation, and generates three bits in a second clock cycle indicative of whether said second instruction is a floating-point operation, a system operation a branch operation or an integer operation; a first set of latches, coupled to said decoder means for storing during said first clock cycle said three bits from said first instruction and for storing during said second clock cycle said three bits from said second instruction; a second set of latches, coupled to said first set of latches, for storing during said second clock cycle said three bits from said first instruction; logic means, coupled to said first and second set of latches, for generating an active bundle signal, wherein said active bundle signal indicates that said first and second instructions will be executed simultaneously when: (a) said first and second instructions are integer instructions, (b) said first instruction is a floating-point operation and said second instruction is an integer instruction, or (c) said first instruction is floating point operation and said second instruction is a branch instruction.
Claim 3
Dependent Claim
188 words
The predecoder unit of claim 1 wherein said logic means includes: a NOR gate having a first input terminal coupled to said first set of latches to receive a bit indicating whether said second instruction is a system instruction and having second and third input terminals coupled to said second set of latches to receive a bit indicating whether said first instruction is a branch instruction and a bit indicating whether said first instruction is a floating-point operation, wherein said NOR gate produces an output signal based on said received bits; an exclusive OR gate having a first input terminal coupled to said first set of latches to receive a bit indicating whether said second instruction is a floating-point operation, having a second input terminal coupled to said second set of latches to receive a bit indicating whether said first instruction is a floating-point operation, wherein said exclusive OR gate produces an output signal based on said received bits; and a NAND gate to receive output signals received from said NOR gate and said exclusive OR gate and to generate said bundle signal based on said received signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |