US5337270A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor dynamic memory
Assignee: Micron Memory Japan Ltd
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Filing: 1992-08-26
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Granted: 1994-08-09
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Expires: 2012-08-26
Abstract
Abstract A DRAM according to the invention is provided with a memory cell array formed by arranging in the row and column directions one-transistor-one-capacitor type memory cells; bit lines, precharged at a prescribed timing, for performing the transfers of write-in/read-out data to and from the memory cells; a sense amplifier including a first transistor, whose drains are connected to the bit lines to bias the substrate to a prescribed potential, and a second transistor whose drains and sources are connected to the sources of the first transistor and a ground potential point, respectively, whose gates receive an activation control signal and whose substrate is biased to the same potential as the first transistor is, for amplifying the signals of said bit lines when activated; an intermediate potential generating circuit for supplying an intermediate potential which is substantially equal to 1/2 of the source potential to the opposite electrodes of said memories and to the bit lines; a power turn-on sensing circuit for generating a sensing signal which takes on an active level after the source potential reaches a prescribed level; and intermediate potential supply control means responsive to the sensing signal for controlling the supply of the intermediate potential to the bit lines. The current sources of said first and second transistors are cut off, power consumption is thereby saved and the occurrence of a latch-up phenomenon suppressed by suspending the supply of the intermediate potential to the bit lines during the period in which, immediately after the power is turned on, the substrate potential rises and the threshold values of the first and second transistors drop to keep these transistors in an ON state.
Inventors
- 👤 Koji Kawata
- 👤 Tadahiko Sugibayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/409; G11C11/4091; G11C11/4094
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
376 words
A dynamic RAM having: a memory cell array formed by arranging memory cells, each including a switching transistor and a capacitance element one of whose electrodes is connected to one each of the source and drain electrodes of this switching transistor, in rows and columns; word lines connected to the gate electrodes of said switching transistors for selecting a memory cell for each of said rows; bit lines connected to the other sources and drain electrodes of said switching transistors, for performing transfers of write-in/read-out data between said memory cells for each of said columns; an intermediate potential generating circuit for generating an intermediate potential which is substantially equal to 1/2 of a source potential supplied from a power supply terminal, supplying it to the other electrodes of said cell capacitance elements and further supplying it to a precharging potential line; a precharging circuit coupled between said bit lines and a circuit node for precharging said bit lines with a potential at said circuit node at a prescribed timing; a sense amplifier, including a first transistor having a drain electrode connected to a first one of said bit lines, a gate electrode connected to a second one of said bit lines and a substrate receiving a prescribed potential, and a second transistor having a drain and a source electrode respectively connected to a source electrode of said first transistor and a ground potential point, a gate electrode receiving an activation control signal and a substrate receiving said prescribed potential, for amplifying variations of the potentials of said bit lines; a power supply turn-on sensing circuit for generating a power-ON sensing signal which takes an inactive level in response to the source potential to said power terminal being turned on, holds said inactive level until the source potential reaches a predetermined level and changes to an active level after the source potential reaches said predetermined level; and intermediate potential supply control means coupled between said precharging potential line and said circuit node for preventing said intermediate potential from being supplied to said circuit node when said power-ON sensing signal is at said inactive level and for allowing said precharging potential to be supplied to said circuit node when said power-ON sensing signal is at said active level.
Claim 2
Dependent Claim
376 words
A dynamic RAM having: a memory cell array formed by arranging memory cells, each including a switching transistor and a capacitance element one of whose electrodes is connected to one each of the source and drain electrodes of this switching transistor, in rows and columns; word lines connected to the gate electrodes of said switching transistors for selecting a memory cell for each of said rows; bit lines connected to the other sources and drain electrodes of said switching transistors, for performing transfers of write-in/read-out data between said memory cells for each of said columns; an intermediate potential generating circuit for generating an intermediate potential which is substantially equal to 1/2 of a source potential supplied from a power supply terminal, supplying it to the other electrodes of said cell capacitance elements and further supplying it to a precharging potential line; a precharging circuit coupled between said bit lines and a circuit node for precharging said bit lines with a potential at said circuit node at a prescribed timing; a sense amplifier, including a first transistor having a drain electrode connected to a first one of said bit lines, a gate electrode connected to a second one of said bit lines and a substrate receiving a prescribed potential, and a second transistor having a drain and a source electrode respectively connected to a source electrode of said first transistor and a ground potential point, a gate electrode receiving an activation control signal and a substrate receiving said prescribed potential, for amplifying variations of the potentials of said bit lines; a power supply turn-on sensing circuit for generating a power-ON sensing signal which takes an inactive level in response to the source potential to said power terminal being turned on, holds said inactive level until the source potential reaches a predetermined level and changes to an active level after the source potential reaches said predetermined level; and intermediate potential supply control means coupled between said precharging potential line and said circuit node for preventing said intermediate potential from being supplied to said circuit node when said power-ON sensing signal is at said inactive level and for allowing said precharging potential to be supplied to said circuit node when said power-ON sensing signal is at said active level.
Claim 3
Dependent Claim
40 words
A dynamic RAM as claimed in claim 1, wherein said intermediate supply control means consists of a third transistor connected between said precharging potential line and said circuit node and supplied at a gate thereof with said power-ON sensing signal.
Claim 4
Dependent Claim
44 words
A dynamic RAM as claimed in claim 2, wherein said third transistor is of the same conductivity type as the first and second transistors of said sense amplifier, and is formed on a substrate separated from the substrate of these first and second transistors.
Claim 5
Dependent Claim
22 words
A dynamic RAM as claimed in claim 3, wherein the substrate of said third transistor is connected to the ground potential point.
Claim 6
Dependent Claim
31 words
A dynamic RAM as claimed in claim 2, wherein said third transistor is a transistor formed on a substrate of a conductivity opposite to that of said first and second transistors.
Claim 7
Dependent Claim
113 words
A dynamic RAM as claimed in claim 1, wherein said intermediate potential generating circuit includes intermediate potential supply control means consisting of an intermediate potential generating section for supplying an intermediate potential which is substantially equal to 1/2 of the source potential supplied from said power supply terminal, a fourth transistor connected between an intermediate potential output end of said intermediate potential generating section and the other of said electrodes of said capacitance elements and a gate supplied with said source potential, and a fifth transistor connected between the intermediate potential output end of said intermediate potential generating section and said precharging potential line and having a gate supplied with said source potential.
Claim 8
Dependent Claim
251 words
A random access memory device, comprising: a memory cell array including: a plurality of word lines; a plurality of pairs of bit lines; and a plurality of memory cells each disposed on a different one of intersections of said word and bit lines; a plurality of sense amplifiers provided correspondingly to said pairs of bit lines; a plurality of precharging circuits provided correspondingly to said pairs of bit lines, each of said precharging circuits being coupled to an associated one of said pairs of bit lines and a first node to precharge said associated one of said pairs of bit lines with a potential level on said first node; a voltage generator generating and supplying an intermediate voltage of a power voltage to a second node; a power-on detection circuit generating a control signal which takes an inactive level in response to said power voltage being turned on, holds said inactive level until said power voltage reaches a predetermined level and changes to an active level after said power voltage reaches said predetermined level; and a first transistor connected between said first and second nodes and supplied with said control signal, said transistor being rendered nonconductive in response to said inactive level of said control signal to prevent said intermediate voltage from being transferred from said second node to said first node and rendered conductive in response to said active level of said control signal to allow said intermediate voltage to be transferred from said second node to said first node.
Claim 9
Dependent Claim
251 words
A random access memory device, comprising: a memory cell array including: a plurality of word lines; a plurality of pairs of bit lines; and a plurality of memory cells each disposed on a different one of intersections of said word and bit lines; a plurality of sense amplifiers provided correspondingly to said pairs of bit lines; a plurality of precharging circuits provided correspondingly to said pairs of bit lines, each of said precharging circuits being coupled to an associated one of said pairs of bit lines and a first node to precharge said associated one of said pairs of bit lines with a potential level on said first node; a voltage generator generating and supplying an intermediate voltage of a power voltage to a second node; a power-on detection circuit generating a control signal which takes an inactive level in response to said power voltage being turned on, holds said inactive level until said power voltage reaches a predetermined level and changes to an active level after said power voltage reaches said predetermined level; and a first transistor connected between said first and second nodes and supplied with said control signal, said transistor being rendered nonconductive in response to said inactive level of said control signal to prevent said intermediate voltage from being transferred from said second node to said first node and rendered conductive in response to said active level of said control signal to allow said intermediate voltage to be transferred from said second node to said first node.
Claim 10
Dependent Claim
60 words
The memory device as claimed in claim 7, wherein each of said memory cells includes a transfer gate transistor and a capacitor connected in series between an associated one of said bit lines and a potential node supplied with said intermediate voltage and wherein said transfer gate transistor has a gate connected to an associated one of said word lines.
Claim 11
Dependent Claim
64 words
The memory device as claimed in claim 8, wherein each of said sense amplifiers includes second and third transistors cross-coupled between an associated pair of said pairs of bit lines, and wherein said memory device further comprises a substrate voltage generator responding to said power voltage and generating a substrate voltage, said substrate voltage being supplied to substrates of said second and third transistors.
Claim 12
Dependent Claim
25 words
The memory device as claimed in claim 9, wherein each of said first, second and third transistors has a channel type equal to one another.
Claim 13
Dependent Claim
29 words
The memory device as claimed in claim 9, wherein said first transistor has one channel type and each of said second and third transistors has an opposite channel type.
References Cited (Backward Citations)
US4965769A
Cited
US4943960A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |