US5336912A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buried plate type DRAM
Assignee: Toshiba Corp
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Filing: 1993-07-13
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Granted: 1994-08-09
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Expires: 2013-07-13
Abstract
Abstract A trench of a buried plate type DRAM has a bottom portion wider than an opening portion. A silicon oxide film is formed on an upper portion of the side wall of the trench. An N-type impurity diffusion region is formed around the bottom portion of the trench. Impurity diffusion regions of adjacent trenches are integrally connected with each other as one portion. A first polycrystalline silicon layer is formed on the impurity diffusion region in the trench and the silicon oxide film. The polycrystalline silicon layer is coated with a laminated film consisting of a silicon nitride film and a silicon oxide film. The trench is filled with a second polycrystalline silicon layer covering the laminated film. The impurity diffusion region serves as a plate diffusion region of a capacitor, the first polycrystalline silicon layer serves as a plate electrode, the laminated film serves as a capacitor insulating film, and the second polycrystalline silicon layer serves as a storage node electrode. The capacitor is formed in the trench.
Inventors
- 👤 Sumito Ohtsuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:20
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/37; H10B12/373; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10D1/68
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
109 words
A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a trench formed in a main surface of the semiconductor substrate and having a region wider than an opening portion thereof; a first insulating layer formed on a side wall of the trench; an impurity diffusion region of a second conductivity type formed around a bottom portion of the trench in the semiconductor substrate; a first conductive layer formed on the impurity diffusion region and the first insulating layer in the trench; a second insulating layer covering the first conductive layer; and a second conductive layer covering the second insulating layer and filled in the trench.
Claim 2
Dependent Claim
109 words
A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a trench formed in a main surface of the semiconductor substrate and having a region wider than an opening portion thereof; a first insulating layer formed on a side wall of the trench; an impurity diffusion region of a second conductivity type formed around a bottom portion of the trench in the semiconductor substrate; a first conductive layer formed on the impurity diffusion region and the first insulating layer in the trench; a second insulating layer covering the first conductive layer; and a second conductive layer covering the second insulating layer and filled in the trench.
Claim 3
Dependent Claim
67 words
A semiconductor memory device according to claim 1, wherein the impurity diffusion region serves as a plate diffusion region of a capacitor, the first conductive layer serves as a plate electrode of the capacitor, the second insulating layer serves as an insulating film of the capacitor, the second conductive layer serves as a storage node electrode of the capacitor, and the capacitor is formed in the trench.
Claim 4
Dependent Claim
24 words
A semiconductor memory device according to claim 2, further comprising a selection MOS transistor formed in the semiconductor substrate and connected to the capacitor.
Claim 5
Dependent Claim
63 words
A semiconductor memory device according to claim 3, wherein the MOS transistor includes source and drain regions formed in the semiconductor substrate, a gate insulating film formed between the source and drain regions on the semiconductor substrate, and a gate electrode formed on the gate insulating film, and one of the source and drain regions is electrically connected to the second conductive layer.
Claim 6
Dependent Claim
125 words
A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a plurality of trenches, spaced apart from each other, formed in a main surface of the semiconductor substrate, each of the trenches having a region wider than an opening portion thereof; a plurality of first insulating layers formed on side walls of the trenches; an impurity diffusion region of a second conductivity type formed around bottom portions of the trenches in the semiconductor substrate; a plurality of first conductive layers formed on the impurity diffusion region and the first insulating layers in the trenches; a plurality of second insulating layers covering the first conductive layers; and a plurality of second conductive layers covering the second insulating layers and filled in the trenches.
Claim 7
Dependent Claim
125 words
A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; a plurality of trenches, spaced apart from each other, formed in a main surface of the semiconductor substrate, each of the trenches having a region wider than an opening portion thereof; a plurality of first insulating layers formed on side walls of the trenches; an impurity diffusion region of a second conductivity type formed around bottom portions of the trenches in the semiconductor substrate; a plurality of first conductive layers formed on the impurity diffusion region and the first insulating layers in the trenches; a plurality of second insulating layers covering the first conductive layers; and a plurality of second conductive layers covering the second insulating layers and filled in the trenches.
Claim 8
Dependent Claim
67 words
A semiconductor memory device according to claim 5, wherein the impurity diffusion region serves as a plate diffusion region of a plurality of capacitors, the first conductive layers serve as plate electrodes of the capacitor, the second insulating layers serve as insulating films of the capacitors, the second conductive layers serve as storage node electrodes of the capacitors, and the capacitors are formed in the respective trenches.
Claim 9
Dependent Claim
27 words
A semiconductor memory device according to claim 6, further comprising a plurality of selection MOS transistors formed in the semiconductor substrate and connected to the respective capacitors.
Claim 10
Dependent Claim
67 words
A semiconductor memory device according to claim 7, wherein each of the MOS transistors includes source and drain regions formed in the semiconductor substrate, a gate insulating film formed between the source and drain regions on the semiconductor substrate, and a gate electrode formed on the gate insulating film, and one of the source and drain regions is electrically connected to one of the second conductive layers.
References Cited (Backward Citations)
JPS60176265A
Cited
JPS60245161A
Cited
US4763179A
Cited
JPS6240759A
Cited
US5079615A
Cited
JPH04107858A
Cited
JPH04287366A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |