General purpose parallel port interface

Claim 2

A general purpose interface for connecting a mass memory storage device to a parallel port of a personal computer for facilitating data transfer between the storage device and a central processing unit of the personal computer, comprising: a cable for connection to the parallel port of the personal computer to transfer data, CPU control and status signals to and from the personal computer; a peripheral port for connection to a peripheral controller for the mass memory storage device to transfer data and interface control signals to and from the peripheral controller; a random access memory circuit for storing the data to be transferred between the storage device and the personal computer; a logic circuit electrically coupled to said cable, said peripheral port and said memory circuit, including decoding means for decoding the CPU control signals from said personal computer and control means responsive to the decoded CPU control signals for generating the interface control signals to said memory circuit and said peripheral port to control transfer of data between any of said cable, said peripheral port and said memory circuit, said control means including a direct memory access channel to control transmission of data between said memory circuit and either said peripheral port or said cable.

Claim 3

The general purpose interface of claim 1 wherein said logic circuit includes a data bus for transferring data between any of said cable, said peripheral port and said memory circuit.

Claim 4

The general purpose interface of claim 2 wherein said data bus is an 8 bit data bus and further comprising a latch circuit controlled by said control means for controlling transfer of data from said data output lines of the parallel port via said cable to said data bus.

Claim 5

The general purpose interface of claim 2 wherein said data bus is an 8 bit data bus and further comprising a multiplex circuit controlled by said control means for controlling transfer of data from said data bus via said cable to status input lines of the parallel port.

Claim 6

The general purpose interface of claim 1 further comprising a floppy disk drive including a floppy disk controller operatively connected to said peripheral port.

Claim 7

The general purpose interface of claim 5 further comprising a housing for housing said floppy disk drive, said peripheral port, said memory circuit and said logic circuit and wherein said cable extends outwardly from said housing.

Claim 8

The general purpose interface of claim 1 wherein said direct memory access channel comprises a counter circuit controlled by said control means for counting amounts of data transferred from said memory circuit to said cable or said peripheral port.

Claim 9

The general purpose interface of claim 1 wherein said memory circuit comprises a dynamic random access memory circuit.

Claim 10

A general purpose interface for connecting a mass memory storage device to a parallel port of a personal computer for facilitating data transfer between the storage device and a central processing unit of the personal computer, comprising: a connector for connection to the parallel port of the personal computer to transfer data and CPU control signals to and from the personal computer; a peripheral port for connection to a peripheral controller for the mass memory storage device to transfer data and interface control signals to and from the peripheral controller; a random access memory circuit for storing the data to be transferred between the storage device and the personal computer; a logic circuit electrically coupled to said connector, said peripheral port and said memory circuit, including decoding means for decoding the CPU control signals from the personal computer, control means responsive to the decoded CPU control signals for generating the interface control signals to said memory circuit and said peripheral port to control transfer of data between any of said connector, said peripheral port and said memory circuit, said control means including a direct memory access channel to control transmission of data between said memory circuit and either said peripheral port or said connector.

Claim 11

A general purpose interface for connecting a mass memory storage device to a parallel port of a personal computer for facilitating data transfer between the storage device and a central processing unit of the personal computer, comprising: a connector for connection to the parallel port of the personal computer to transfer data and CPU control signals to and from the personal computer; a peripheral port for connection to a peripheral controller for the mass memory storage device to transfer data and interface control signals to and from the peripheral controller; a random access memory circuit for storing the data to be transferred between the storage device and the personal computer; a logic circuit electrically coupled to said connector, said peripheral port and said memory circuit, including decoding means for decoding the CPU control signals from the personal computer, control means responsive to the decoded CPU control signals for generating the interface control signals to said memory circuit and said peripheral port to control transfer of data between any of said connector, said peripheral port and said memory circuit, said control means including a direct memory access channel to control transmission of data between said memory circuit and either said peripheral port or said connector.

Claim 12

The general purpose interface of claim 9 wherein said logic circuit includes a data bus for transferring data between any of said connector, said peripheral port and said memory circuit.

Claim 13

The general purpose interface of claim 10 wherein said data bus is an 8 bit data bus and further comprising a latch circuit controlled by said control means for controlling transfer of data from data output lines of the parallel port via said connector to said data bus.

Claim 14

The general purpose interface of claim 10 wherein said data bus is an 8 bit data bus and further comprising a multiplex circuit controlled by said control means for controlling transfer of data from said data bus via said connector to status input lines of the parallel port.

Claim 15

The general purpose interface of claim 9 further comprising a floppy disk drive including a floppy disk controller operatively connected to said peripheral port.

Claim 16

The general purpose interface of claim 9 further comprising a housing for housing said floppy disk drive, said peripheral port, said memory circuit and said logic circuit and a cable extending outwardly from said housing for connecting said connector to the parallel port.

Claim 17

The general purpose interface of claim 9 wherein said direct memory access channel comprises a counter circuit controlled by said control means for counting amounts of data transferred from said memory circuit to said connector or said peripheral port.

Claim 18

The general purpose interface of claim 9 wherein said memory circuit comprises a dynamic random access memory circuit.

Claim 19

A general purpose interface for connecting a mass memory storage device to a parallel port of a personal computer for facilitating data transfer between the storage device and a central processing unit of the personal computer, comprising: a first connector for connection to the parallel port of the personal computer to transfer data and CPU control signals to and from the personal computer; a second connector for connection to the parallel peripheral device; a peripheral port for connection to a peripheral controller for the mass memory storage device to transfer data and interface control signals to and from the peripheral controller; a random access memory circuit for storing data to be transferred between the storage device and the personal computer; a logic circuit electrically coupled to said first and second connectors, said peripheral port and said memory circuit, including decoding means for decoding the CPU control signals from the personal computer, control means responsive to the decoded CPU control signals for generating the interface control signals to said memory circuit and said peripheral port to control transfer of data between any of said connector, said peripheral port and said memory circuit, and feedthrough means controlled by said control means for operatively connecting said first and second connectors together if no command is received by said decoding means.

Claim 20

A general purpose interface for connecting a mass memory storage device to a parallel port of a personal computer for facilitating data transfer between the storage device and a central processing unit of the personal computer, comprising: a first connector for connection to the parallel port of the personal computer to transfer data and CPU control signals to and from the personal computer; a second connector for connection to the parallel peripheral device; a peripheral port for connection to a peripheral controller for the mass memory storage device to transfer data and interface control signals to and from the peripheral controller; a random access memory circuit for storing data to be transferred between the storage device and the personal computer; a logic circuit electrically coupled to said first and second connectors, said peripheral port and said memory circuit, including decoding means for decoding the CPU control signals from the personal computer, control means responsive to the decoded CPU control signals for generating the interface control signals to said memory circuit and said peripheral port to control transfer of data between any of said connector, said peripheral port and said memory circuit, and feedthrough means controlled by said control means for operatively connecting said first and second connectors together if no command is received by said decoding means.

Claim 21

The general purpose interface of claim 17 further comprising a floppy disk drive including a floppy disk controller operatively connected to said peripheral port.

Claim 22

The general purpose interface of claim 18 further comprising a housing for housing said floppy disk drive, said peripheral port, said memory circuit, said second connector and said logic circuit and a cable extending outwardly from said housing for connecting said first connector to the parallel port.

Claim 23

The general purpose interface of claim 17 wherein said memory circuit comprises a dynamic random access memory circuit.