Patent US5335200A successfully refreshed from Google Patents.
← Back to Patent Explorer
US5335200A Expired / Lapsed US ⏱️ 0.0 years remaining

High voltage negative charge pump with low voltage CMOS transistors

Assignee: Texas Instruments Inc
•
Filing: 1993-01-05
•
Granted: 1994-08-02
•
Expires: 2013-01-05
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An improved negative charge pump system for erasing a memory array in a memory which has a supply voltage and a negative charge pump. The negative charge pump system includes (a) a device for selecting a memory array to be erased; (b) a device for switching on the supply voltage Vnn for the charge pump; (c) a device for pumping the supply voltage Vnn with the charge pump to produce a pumped negative voltage; (d) a device for erasing the selected array with the pumped negative voltage; (e) a device for stopping the pumping; and (f) a device for providing a discharge path for voltages trapped in the charge pump.

Inventors

  • 👤 Tim M. Coffman
  • 👤 Sung-Wei Lin

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 07:39
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/14; G11C16/30; G11C5/00; G11C5/14; G11C5/145

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 101 words
A method for erasing a memory array in a memory which has a supply voltage and a negative charge having multiple stages, comprising the steps of: (a) selecting a memory array to be erased; (b) applying the supply voltage to the charge pump; (c) pumping the supply voltage to produce a pumped negative voltage from a negative at each of said multiple stages of said negative charge pump; (d) erasing the selected array with the pumped negative voltage; (e) stopping said erasing; and (f) providing a separate discharge path for the negative voltage trapped in each stage of the charge pump.
Claim 2
Independent Claim 101 words
A method for erasing a memory array in a memory which has a supply voltage and a negative charge having multiple stages, comprising the steps of: (a) selecting a memory array to be erased; (b) applying the supply voltage to the charge pump; (c) pumping the supply voltage to produce a pumped negative voltage from a negative at each of said multiple stages of said negative charge pump; (d) erasing the selected array with the pumped negative voltage; (e) stopping said erasing; and (f) providing a separate discharge path for the negative voltage trapped in each stage of the charge pump.
Claim 3
Dependent Claim 119 words
An improved negative charge pump system for erasing a memory array in a memory which has a supply voltage and a negative charge pump having multiple stages, comprising: (a) means for selecting a memory array to be erased; (b) means for applying the supply voltage to the charge pump; (c) means for pumping the supply voltage to produce a pumped negative voltage from a negative voltage at each of said multiple stages of said negative charge pump; (d) means for erasing the selecting array with the pumped negative voltage; (e) means for stopping said erasing; and (f) means for providing a separate discharge path for each of said negative voltages trapped in each said stage of the charge pump.
Claim 4
Dependent Claim 119 words
An improved negative charge pump system for erasing a memory array in a memory which has a supply voltage and a negative charge pump having multiple stages, comprising: (a) means for selecting a memory array to be erased; (b) means for applying the supply voltage to the charge pump; (c) means for pumping the supply voltage to produce a pumped negative voltage from a negative voltage at each of said multiple stages of said negative charge pump; (d) means for erasing the selecting array with the pumped negative voltage; (e) means for stopping said erasing; and (f) means for providing a separate discharge path for each of said negative voltages trapped in each said stage of the charge pump.

References Cited (Backward Citations)

US4752699A Cited
US5077691A Cited
US5126808A Cited
US5235544A Cited
US5168174A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-08-01 1998-01-31 1998-08-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-08-01 2002-01-31 2002-08-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-08-01 2006-01-31 2006-08-02 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag