Patent US5335105A successfully refreshed from Google Patents.
US5335105A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed communications interface protection system
Assignee: Nokia of America Corp
•
Filing: 1992-04-10
•
Granted: 1994-08-02
•
Expires: 2012-04-10
Abstract
Abstract Working DS3/STS interface cards (18, 46) receive DS3 traffic on incoming DS3 communication lines (12, 42). The interface cards (18, 46) are operable to translate the DS3 signals into STS signals, and to "stuff" them into "A" and "B" clock frames provided to them by an "A" formatter (70) and a "B" formatter (74). These clock frames are then used to transmit data to the "A" formatter (70) and the "B" formatter (74). The DS3/STS interface cards (18,46) inspect incoming STS signals on "A" and "B" buses (82, 84) without having to switch to the inspected signal. Formatters 70 and 74 translate the STS data into formatted data, which eventually are transmitted in optical form on respective optical fibers (150, 190) at clock rates which do not have to be the same. Regeneration input and output ports ( 210, 216, 206, 166) allow the through-communication of telecommunications signals in STS format, obviating the need for down-translation to DS3 format and back-translation to STS format.
Inventors
- 👤 Stephen C. Carlton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:53
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/14; H04J2203/00; H04J2203/0001; H04J2203/0089
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
A high speed telecommunications interface protection system, comprising: at least one interface circuit operable to receive a first signal in a first protocol and in response thereto to transmit a second signal in a second protocol, said interface circuit further operable to receive a third signal in said second protocol and in response thereto to transmit a fourth signal in said first protocol; a first destination circuit coupled to said interface circuit, said first destination circuit operable to generate a first clock frame and to send said first clock frame to said interface circuit; a second destination circuit coupled to said interface circuit, said second destination circuit operable to generate a second clock frame and to send said second clock frame to said interface circuit; and said interface circuit operable to transmit said second signal in said second protocol to said first destination circuit by inserting said second signal into said first clock frame to said first destination circuit, said interface circuit further operable to transmit said second signal in said second protocol to said second destination circuit by inserting said second signal into said second clock frame and retransmitting said second clock frame to said second destination circuit.
Claim 2
Dependent Claim
199 words
A high speed telecommunications interface protection system, comprising: at least one interface circuit operable to receive a first signal in a first protocol and in response thereto to transmit a second signal in a second protocol, said interface circuit further operable to receive a third signal in said second protocol and in response thereto to transmit a fourth signal in said first protocol; a first destination circuit coupled to said interface circuit, said first destination circuit operable to generate a first clock frame and to send said first clock frame to said interface circuit; a second destination circuit coupled to said interface circuit, said second destination circuit operable to generate a second clock frame and to send said second clock frame to said interface circuit; and said interface circuit operable to transmit said second signal in said second protocol to said first destination circuit by inserting said second signal into said first clock frame to said first destination circuit, said interface circuit further operable to transmit said second signal in said second protocol to said second destination circuit by inserting said second signal into said second clock frame and retransmitting said second clock frame to said second destination circuit.
Claim 3
Dependent Claim
48 words
The system of claim 1, wherein said first and second destination circuits comprise formatters for formatting said signals in said second protocol into respective formatted signals, respective optical transmitters coupled to said formatters for receiving respective ones of said formatted signals and transmitting optical signals in response thereto.
Claim 4
Dependent Claim
131 words
The system of claim 1, and further comprising first and second source circuits coupled to said interface circuit for transmitting signals in said second protocol to said interface circuit, said first source circuit transmitting said third signal to said interface circuit as inserted into a first clock frame, said second source circuit transmitting said third signal to said interface circuit as inserted into a second clock frame, at least said first clock frame capable of including alarm signals for signalling a malfunction; said interface circuit normally selecting said third signal from said first source circuit for reception and retransmission in said first protocol, said interface circuit selecting said third signal from said second source circuit in response to sensing an alarm in said clock frame sent from said first source circuit.
Claim 5
Dependent Claim
68 words
The system of claim 3, wherein said first and second source circuits comprise a deformatters operable to deformat a formatted signal into a signal in said second protocol, said system further comprising, for each of said deformatters, an optical receiver operable to receive an optical signal and coupled to a respective one of said deformatters for transmitting thereto a formatted signal in response to receiving said optical signal.
Claim 6
Dependent Claim
16 words
The system of claim 1, wherein said first protocol is DS3, said second protocol being STS.
Claim 7
Independent Claim
162 words
A method for transmitting signals within a telecommunications interface using at least first and second telecommunications protocols, comprising the steps of: receiving data in said first communications protocol by at least one interface circuit; translating said received data by said interface circuit into data in said second communications protocol; using an "A" clock of an "A" destination circuit, generating an "A" clock frame; using a "B" clock of a "B" destination circuit, generating a "B" clock frame, the "A" clock and the "B" clock not having to be synchronized; transmitting from the "A" destination circuit to the interface circuit the "A" clock frame; transmitting from the "B" destination circuit to the interface circuit the "B" clock frame; using the "A" clock frame, transmitting the data in said second communications protocol from the interface circuit to said "A" destination circuit; and using the "B" clock frame, transmitting the data in said second communications protocol from the interface circuit to said "B" destination circuit.
Claim 8
Independent Claim
162 words
A method for transmitting signals within a telecommunications interface using at least first and second telecommunications protocols, comprising the steps of: receiving data in said first communications protocol by at least one interface circuit; translating said received data by said interface circuit into data in said second communications protocol; using an "A" clock of an "A" destination circuit, generating an "A" clock frame; using a "B" clock of a "B" destination circuit, generating a "B" clock frame, the "A" clock and the "B" clock not having to be synchronized; transmitting from the "A" destination circuit to the interface circuit the "A" clock frame; transmitting from the "B" destination circuit to the interface circuit the "B" clock frame; using the "A" clock frame, transmitting the data in said second communications protocol from the interface circuit to said "A" destination circuit; and using the "B" clock frame, transmitting the data in said second communications protocol from the interface circuit to said "B" destination circuit.
Claim 9
Dependent Claim
19 words
The method of claim 6, wherein said first communications protocol is DS3 and the second communications protocol is STS.
Claim 10
Dependent Claim
54 words
The method of claim 6, wherein said "A" and "B" destination circuits are each coupled to an optical communications fiber, the method further including the step of transmitting an optical signal on each said fiber in response to corresponding ones of said "A" and "B" destination circuits receiving data in said second communications protocol.
References Cited (Backward Citations)
US4967405A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-01 | 1998-01-31 | 1998-08-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-01 | 2002-01-31 | 2002-08-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-01 | 2006-01-31 | 2006-08-02 | $7700.00 | Window Closed / Lapsed |