Patent US5333300A successfully refreshed from Google Patents.
US5333300A
Expired / Lapsed
US
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Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory
Assignee: Intel Corp
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Filing: 1991-02-11
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Granted: 1994-07-26
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Expires: 2011-02-11
Abstract
Abstract Circuitry for handshaking between a command state machine and write state machine is described. The handshaking circuitry, the command state machine and the write state machine are part of a non-volatile semiconductor memory device that includes a memory array. The command state machine receives commands from a user and communicates valid commands to the write state machine, which responds by performing automated program and erasure operations on the memory array, as appropriate. The command state machine identifies valid commands based upon signals generated by the handshaking circuitry. The handshaking circuitry includes three latches, an OR gate and a NAND gate. The serially coupled latches store an idle signal from the write state machine. The OR gate is coupled to outputs from the second and third of the serially coupled latches and generates a signal indicative of the whether the write state machine is idle. The NAND gate generates another signal indicative of whether the write state machine is busy based upon a start signal, a finished signal and a delayed idle signal. Also described are a method of handshaking between the write state machine and the command state machine and circuitry for powering up and powering down the write state machine.
Inventors
- 👤 Mickey L. Fandrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:28
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C2216/00; G11C2216/12; G11C2216/20
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
199 words
Handshaking circuitry in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the handshaking circuitry comprising: (a) a first latch for storing an idle signal from the write state machine; (b) a second latch coupled to the first latch; (c) a third latch coupled to the second latch; (d) an OR gate coupled to the first latch and the third latch, the OR gate outputting a signal indicating whether the write state machine is idle; (e) a NAND gate coupled to a start signal, a finished signal and a delayed idle signal, the NAND gate outputting a busy signal for indicating whether the write state machine is busy.
Claim 2
Dependent Claim
199 words
Handshaking circuitry in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the handshaking circuitry comprising: (a) a first latch for storing an idle signal from the write state machine; (b) a second latch coupled to the first latch; (c) a third latch coupled to the second latch; (d) an OR gate coupled to the first latch and the third latch, the OR gate outputting a signal indicating whether the write state machine is idle; (e) a NAND gate coupled to a start signal, a finished signal and a delayed idle signal, the NAND gate outputting a busy signal for indicating whether the write state machine is busy.
Claim 3
Dependent Claim
32 words
The circuitry for handshaking of claim 1, further comprising a NAND gate coupled to the second latch and a suspend signal from the command state machine for generating the delayed idle signal.
Claim 4
Dependent Claim
26 words
The circuitry for handshaking of claim 1 further comprising, an OR gate coupled to a program signal and an erase signal for generating the start signal.
Claim 5
Dependent Claim
200 words
Circuitry for controlling timing of signals between a write state machine and a command state machine in a memory device including the command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the circuitry for controlling the timing of signals between the write state machine and the command state machine comprising: (a) powering up and powering down circuitry for automatically powering up and powering down a clock associated with the write state machine, the clock generating a clock signal; and (b) handshaking circuitry coupled to the write state machine and the command state machine.
Claim 6
Dependent Claim
200 words
Circuitry for controlling timing of signals between a write state machine and a command state machine in a memory device including the command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the circuitry for controlling the timing of signals between the write state machine and the command state machine comprising: (a) powering up and powering down circuitry for automatically powering up and powering down a clock associated with the write state machine, the clock generating a clock signal; and (b) handshaking circuitry coupled to the write state machine and the command state machine.
Claim 7
Dependent Claim
24 words
The circuitry of claim 4, further comprising a means for synchronizing a suspend command from command state machine to clock signals from the clock.
Claim 8
Dependent Claim
51 words
The circuitry of claim 4 wherein the means for automatically powering up and powering down a clock comprises: (a) means for starting the clock in response to a start signal; (b) a latch for stopping the clock in response to a stop signal, wherein the latch is clocked by the clock.
Claim 9
Dependent Claim
145 words
Circuitry for stopping a write state machine in a memory device including a command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the circuitry for stopping the write state machine comprising: (a) circuitry for powering up a clock, the clock outputting a clock signal, the clock signal being coupled to the write state machine; and (b) a latch for powering down the clock in response to a stop signal, wherein the latch is clocked by the clock signal.
Claim 10
Dependent Claim
145 words
Circuitry for stopping a write state machine in a memory device including a command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the circuitry for stopping the write state machine comprising: (a) circuitry for powering up a clock, the clock outputting a clock signal, the clock signal being coupled to the write state machine; and (b) a latch for powering down the clock in response to a stop signal, wherein the latch is clocked by the clock signal.
Claim 11
Dependent Claim
17 words
The circuit of claim 7 further comprising means for decoding status signals to generate the stop signal.
Claim 12
Dependent Claim
153 words
Circuitry for powering up and powering down a write state machine in a memory device including a command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the circuitry for powering up and powering down the write state machine comprising: (a) a first latch for storing a stop signal; (b) a second latch coupled to the first latch wherein the second latch is clocked by a clock coupled to the write state machine; and (c) an AND gate coupled to the second latch and a start signal.
Claim 13
Dependent Claim
153 words
Circuitry for powering up and powering down a write state machine in a memory device including a command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to a handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the circuitry for powering up and powering down the write state machine comprising: (a) a first latch for storing a stop signal; (b) a second latch coupled to the first latch wherein the second latch is clocked by a clock coupled to the write state machine; and (c) an AND gate coupled to the second latch and a start signal.
Claim 14
Dependent Claim
16 words
The circuitry of claim 9, further comprising a decoder generating the stop signal from status signals.
Claim 15
Dependent Claim
29 words
The circuitry of claim 9, further comprising an OR gate for generating the start signal, wherein the OR gate is coupled to an erase signal and a program signal.
Claim 16
Dependent Claim
15 words
The circuitry of claim 9, wherein the AND gate is coupled to the first latch.
Claim 17
Dependent Claim
395 words
Handshaking circuitry in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the handshaking circuitry comprising: (a) idle signal generator generating an active idle signal in response to an active first signal from the write state machine, the active first signal indicating that the write state machine has paused an operation, the idle signal going active at a first time in response to the first signal being active, the idle signal being coupled to the command state machine; and (b) ready signal generator generating an inactive ready signal in response to an active erase signal, the ready signal being coupled to the command state machine, the ready signal indicating that the write state machine is busy performing an operation on the memory array when the ready signal is inactive, the ready signal being driven active in response to an active suspend signal at a second time after the first time, the second set of commands being enabled at the second time, the ready signal being driven inactive in response to the suspend signal going inactive while the erase signal remains active at a third time after the second time and before a fourth time when the idle signal is driven inactive in response to the suspend signal going inactive, indicating that the erase operation has resumed in response to a resume command, the first set of commands being enabled at the fourth time.
Claim 18
Dependent Claim
395 words
Handshaking circuitry in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, the write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the handshaking circuitry comprising: (a) idle signal generator generating an active idle signal in response to an active first signal from the write state machine, the active first signal indicating that the write state machine has paused an operation, the idle signal going active at a first time in response to the first signal being active, the idle signal being coupled to the command state machine; and (b) ready signal generator generating an inactive ready signal in response to an active erase signal, the ready signal being coupled to the command state machine, the ready signal indicating that the write state machine is busy performing an operation on the memory array when the ready signal is inactive, the ready signal being driven active in response to an active suspend signal at a second time after the first time, the second set of commands being enabled at the second time, the ready signal being driven inactive in response to the suspend signal going inactive while the erase signal remains active at a third time after the second time and before a fourth time when the idle signal is driven inactive in response to the suspend signal going inactive, indicating that the erase operation has resumed in response to a resume command, the first set of commands being enabled at the fourth time.
Claim 19
Dependent Claim
92 words
The circuitry for handshaking of claim 13, the ready signal generator further comprising: circuitry coupled to the erase signal and the suspend signal, the circuitry driving the ready signal inactive whenever the erase signal is active and the suspend signal is inactive, indicating that the write machine is busy performing an operation on the memory array, the circuitry driving the ready signal active whenever the suspend signal is active, indicating that the write machine has suspended the operation on the memory array and may perform a new operation on the memory array.
Claim 20
Dependent Claim
34 words
The circuitry for handshaking of claim 14, wherein commands that can be issued by the command state machine while the write state machine is performing an erase operation include SUSPEND and STATUS REGISTER READ.
Claim 21
Dependent Claim
32 words
The circuitry for handshaking of claim 15, wherein the commands that can be issued when the write state machine has suspended an erase operation include STATUS REGISTER READ, ARRAY READ, and RESUME.
Claim 22
Independent Claim
310 words
A method for handshaking in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, a write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of valid commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the method for handshaking comprising the sequential steps of: (a) indicating that the write state machine has paused an erase operation via an active idle signal; (b) indicating that the write state machine is ready to receive a valid command via an active ready signal, the command state machine being enabled to issue the second set of commands but not being enabled to issue a second erase command; (c) indicating that the write state machine is not ready to receive a command via an inactive ready signal in response to a command from the command state machine to resume the erase operation; and (d) indicating via an inactive idle signal that the write state machine is no longer in the idle state in response to the write state machine resuming the erase operation.
Claim 23
Independent Claim
310 words
A method for handshaking in a memory device including a command state machine, a write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, a write state machine performing operations on the memory array in response to valid commands from the command state machine, the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of valid commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the method for handshaking comprising the sequential steps of: (a) indicating that the write state machine has paused an erase operation via an active idle signal; (b) indicating that the write state machine is ready to receive a valid command via an active ready signal, the command state machine being enabled to issue the second set of commands but not being enabled to issue a second erase command; (c) indicating that the write state machine is not ready to receive a command via an inactive ready signal in response to a command from the command state machine to resume the erase operation; and (d) indicating via an inactive idle signal that the write state machine is no longer in the idle state in response to the write state machine resuming the erase operation.
Claim 24
Dependent Claim
19 words
The method for handshaking of claim 17, wherein the first set of commands includes SUSPEND and STATUS REGISTER READ.
Claim 25
Dependent Claim
21 words
The method for handshaking of claim 18, wherein the second set of commands includes STATUS REGISTER READ, ARRAY READ, and RESUME.
Claim 26
Independent Claim
410 words
A method for controlling timing of signals between a write state machine and a command state machine in a memory device including the command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, a write state machine performing operations on the memory array in response to valid commands from the command state machine,the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of valid commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the method for controlling the timing of signals between the write state machine and the command state machine comprising the sequential steps of: (a) powering up a clock outputting a clock signal in response to the erase command from the command state machine, the clock signal being coupled the write state machine; (b) indicating via an inactive ready signal that the write state machine is not ready in response to the write machine starting the erase operation; (c) indicating that the write state machine has paused an erase operation via an active idle signal; (d) indicating that the write state machine is ready to receive a valid command via an active ready signal, the command state machine being enabled to issue the second set of commands but not being enabled to issue a second erase command; (e) indicating that the write state machine is not ready to receive a command via an inactive ready signal in response to a command from the command state machine to resume the erase operation; (f) indicating via an inactive idle signal that the write state machine is no longer in the idle state in response to the write state machine resuming the erase operation; and (g) powering down the clock substantially near a rising edge of the clock signal in response to a stop signal.
Claim 27
Independent Claim
410 words
A method for controlling timing of signals between a write state machine and a command state machine in a memory device including the command state machine, the write state machine, and a memory array, the command state machine receiving commands from a user, the command state machine communicating valid commands to the write state machine, the command state machine identifying valid commands in response to the handshaking circuitry, a write state machine performing operations on the memory array in response to valid commands from the command state machine,the write state machine indicating its status to the handshaking circuitry, the write state machine performing an erase operation in response to an erase command from the command state machine, the command state machine being able to issue a first set of valid commands while the write state machine is erasing, the write state machine pausing performance of the erase operation in response to a suspend command from the command state machine, the command state machine being able to issue a second set of commands while the write state machine is paused, the second set of commands not including the erase command, the method for controlling the timing of signals between the write state machine and the command state machine comprising the sequential steps of: (a) powering up a clock outputting a clock signal in response to the erase command from the command state machine, the clock signal being coupled the write state machine; (b) indicating via an inactive ready signal that the write state machine is not ready in response to the write machine starting the erase operation; (c) indicating that the write state machine has paused an erase operation via an active idle signal; (d) indicating that the write state machine is ready to receive a valid command via an active ready signal, the command state machine being enabled to issue the second set of commands but not being enabled to issue a second erase command; (e) indicating that the write state machine is not ready to receive a command via an inactive ready signal in response to a command from the command state machine to resume the erase operation; (f) indicating via an inactive idle signal that the write state machine is no longer in the idle state in response to the write state machine resuming the erase operation; and (g) powering down the clock substantially near a rising edge of the clock signal in response to a stop signal.
Claim 28
Dependent Claim
17 words
The method of claim 20, wherein the first set of commands includes SUSPEND and STATUS REGISTER READ.
Claim 29
Dependent Claim
19 words
The method of claim 21, wherein the second set of commands includes STATUS REGISTER READ, ARRAY READ, and RESUME.
Claim 30
Dependent Claim
39 words
The method of claim 22 further comprising the steps of: (a) storing a SUSPEND command from the command state machine; (b) providing the SUSPEND command to the write state machine substantially near the rising edge of the clock signal.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |