Configurable data width direct memory access device with a read address counter and a write address counter which increments the addresses based on the desired data transfer width

Claim 1

A variable width memory access device connected to an n byte wide system data bus, n being at least 2, said variable width memory access device comprising: an n byte wide internal data bus, said internal data bus being organized in n single byte wide lanes; transceiver means having a total width of n bytes and being controllable in single byte increments, said transceiver means being coupled to the system data bus and said internal data bus; data copy means connected between selected byte lanes of said internal data bus for transferring data between said selected byte lanes; memory means having a total width of n bytes and being controllable in single byte increments, said memory means being coupled to said internal data bus and having a plurality of address inputs; means for indicating a desired width of a data transfer; counter means coupled to said desired width indicating means and providing address outputs coupled to said memory means, said counter means incrementing said address outputs based on said desired data transfer width; control means coupled to said counter means, said desired data width means, said memory means, said data copy means and said transceiver means for controlling data transfer through said transceiver means based on said desired data transfer width, through said data copy means based on said desired data width and said address provided by said counter means, and with said memory means based on said desired data width and said address provided by said counter means, so that said each of said memory means byte increments is fully utilized based on each of said desired data transfer widths.