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US5333004A
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Active matrix flat display
Assignee: THOMSON-LCD A Corp OF FRANCE
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Filing: 1991-11-12
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Granted: 1994-07-26
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Expires: 2011-11-12
Abstract
Abstract This invention concerns active matrix flat displays in which the pixels (10) are placed at the intersections between two mutually-perpendicular sets of conductors known as lines (L1 to LN) and columns (C1 to CM). In the invention, each pixel consists of two capacitors (CON1, CON'1) connected in series and consisting of electro-optical components, this circuit being connected between two control transistors (T1, T'1), these two transistors being connected to a common line (L1) and two different columns (C1, C'1) respectively.
Inventors
- 👤 Bruno Mourey
- 👤 Bernard Hepp
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:43
CPC Classifications
G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/13624; G09; G09G; G09G3/00; G09G3/20; G09G3/34; G09G3/36; G09G3/3611; G09G3/3648; G09G3/3659; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0823; G09G2320/00; G09G2320/02; G09G2320/0204; G09G2320/0219
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
106 words
An active matrix flat display in which the pixels (10, 10') are placed at the intersection of two mutually-perpendicular sets of conductors known as rows (L1 to LN) and columns (C1 to CM) in which each pixel comprises a pair of capacitors (CON1, CON'1) connected in series and formed by electro-optical components, this pair of capacitors being connected between two control transistors (T1, T'1), these transistors being connected to a common row (L1) and to two different columns respectively (C1, C'1 or C01, C'01, C'01), each individual pixel further comprising an individual counter electrode which is common only to the two capacitors contained in the pixel.
Claim 2
Dependent Claim
106 words
An active matrix flat display in which the pixels (10, 10') are placed at the intersection of two mutually-perpendicular sets of conductors known as rows (L1 to LN) and columns (C1 to CM) in which each pixel comprises a pair of capacitors (CON1, CON'1) connected in series and formed by electro-optical components, this pair of capacitors being connected between two control transistors (T1, T'1), these transistors being connected to a common row (L1) and to two different columns respectively (C1, C'1 or C01, C'01, C'01), each individual pixel further comprising an individual counter electrode which is common only to the two capacitors contained in the pixel.
Claim 3
Dependent Claim
37 words
A flat display as described in claim 1 in which each pixel (10) is connected to two columns (C1, C'1) with a data voltage VD and an inverse data voltage -VD applied to these two columns respectively.
Claim 4
Dependent Claim
18 words
A flat display as described in claim 2 in which voltages VD and -VD reverse at each frame.
Claim 5
Dependent Claim
35 words
A flat display as described in claim 1 in which each pair of adjacent pixels (10, 10') on a line is connected to a common column (C'01 to which a fixed DC voltage is applied.
Claim 6
Dependent Claim
18 words
A flat display as described in claim 4 in which the fixed DC voltage is the counter-electrode voltage.
Claim 7
Dependent Claim
16 words
A flat display as described in claim 1 in which the electro-optical components are liquid crystals.
References Cited (Backward Citations)
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US4753518A
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JPS6331825A
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JPH0273234A
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US5159476A
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JPH03196019A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |