Auto-reset circuit with improved testability

Claim 2

An auto-reset circuit for generating a power-up reset signal, comprising: a first power-supply terminal for receiving a first potential; a second power-supply terminal for receiving a second potential different from said first potential; an output terminal for output of the reset signal; a first active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said first power-supply terminal, the third terminal being coupled to said second power-supply terminal; a first resistor coupled between the second terminal of the first active element and said second power-supply terminal; a second resistor coupled between said first power-supply terminal and said output terminal; a second active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said second power-supply terminal, the second terminal being coupled to said output terminal, and the third terminal being coupled to the second terminal of the first active element; a third resistor coupled between the second terminal of the first active element and the third terminal of the second active element; and a capacitor coupled between the third terminal of the second active element and said second power-supply terminal.

Claim 3

The circuit of claim 1, further comprising a diode via which the third terminal of said second active element is coupled to said first power-supply terminal.

Claim 4

The circuit of claim 2, further comprising a fourth resistor coupled in series between the second terminal of the first active element and said first resistor, said fourth resistor also being coupled in series between the second terminal of said first active element and said third resistor.

Claim 5

The circuit of claim 1, further comprising a fourth resistor coupled in series between the second terminal of the first active element and said first resistor, said fourth resistor also being coupled in series between the second terminal of said first active element and said third resistor.

Claim 6

An auto-reset circuit for generating a power-up reset signal, comprising; a first power-supply terminal for receiving a first potential; a second power-supply terminal for receiving a second potential different from said first potential; an output terminal for output of the reset signal; a first control signal input terminal for input of a first control signal to halt current flow during static current measurements; a first active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said first power-supply terminal, and the third terminal being coupled to said first control signal input terminal; a first resistor coupled between the second terminal of the first active element and said second power-supply terminal; a second resistor coupled between said first power-supply terminal and said output terminal; a second active element having first and second terminals, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal of which is coupled to said second power-supply terminal, the second terminal of which is coupled to said output terminal and the third terminal of which is coupled to the second terminal of the first active element; a second control signal input terminal, for input of a second control signal to control output of said reset signal during static current measurements; and a logic gate having input terminals coupled to said output terminal and said second control signal input terminal, for gating said reset signal.

Claim 7

An auto-reset circuit for generating a power-up reset signal, comprising; a first power-supply terminal for receiving a first potential; a second power-supply terminal for receiving a second potential different from said first potential; an output terminal for output of the reset signal; a first control signal input terminal for input of a first control signal to halt current flow during static current measurements; a first active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said first power-supply terminal, and the third terminal being coupled to said first control signal input terminal; a first resistor coupled between the second terminal of the first active element and said second power-supply terminal; a second resistor coupled between said first power-supply terminal and said output terminal; a second active element having first and second terminals, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal of which is coupled to said second power-supply terminal, the second terminal of which is coupled to said output terminal and the third terminal of which is coupled to the second terminal of the first active element; a second control signal input terminal, for input of a second control signal to control output of said reset signal during static current measurements; and a logic gate having input terminals coupled to said output terminal and said second control signal input terminal, for gating said reset signal.

Claim 8

An auto-reset circuit for generating a power-up reset signal, comprising; a first power-supply terminal for receiving a first potential; a second power-supply terminal for receiving a second potential different from said first potential; an output terminal for output of the reset signal; a first control signal input terminal for input of a first control signal to halt current flow during static current measurements; a first active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said first power-supply terminal, and the third terminal being coupled to said first control signal input terminal; a first resistor coupled between the second terminal of the first active element and said second power-supply terminal; a second resistor coupled between said first power-supply terminal and said output terminal; a second active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said second power-supply terminal, the second terminal being coupled to said output terminal, and the third terminal being coupled to the second terminal of the first active element; a third resistor coupled between the second terminal of said first active element and the third terminal of said second active element; and a capacitor coupled between the third terminal of said second active element and said second power-supply terminal.

Claim 9

An auto-reset circuit for generating a power-up reset signal, comprising; a first power-supply terminal for receiving a first potential; a second power-supply terminal for receiving a second potential different from said first potential; an output terminal for output of the reset signal; a first control signal input terminal for input of a first control signal to halt current flow during static current measurements; a first active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said first power-supply terminal, and the third terminal being coupled to said first control signal input terminal; a first resistor coupled between the second terminal of the first active element and said second power-supply terminal; a second resistor coupled between said first power-supply terminal and said output terminal; a second active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said second power-supply terminal, the second terminal being coupled to said output terminal, and the third terminal being coupled to the second terminal of the first active element; a third resistor coupled between the second terminal of said first active element and the third terminal of said second active element; and a capacitor coupled between the third terminal of said second active element and said second power-supply terminal.

Claim 10

The circuit of claim 6, further comprising a third active element having a first terminal, a second terminal, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal of which is coupled to said second power-supply terminal, the second terminal of which is coupled to the third terminal of said second active element, and the third terminal of which is coupled to said first control signal input terminal, for discharging said capacitor prior to static current measurements.

Claim 11

The circuit of claim 7, further comprising a diode via which the third terminal of said second active element is cathode coupled to said first power-supply terminal.

Claim 12

The circuit of claim 8, further comprising a fourth resistor coupled in series between the second terminal of the first active element and said first resistor, said fourth resistor also being coupled in series between the second terminal of said first active element and the third terminal of said second active element.

Claim 13

The circuit of claim 7, further comprising a fourth resistor coupled in series between the second terminal of the first active element and said first resistor, said fourth resistor also being coupled in series between the second terminal of said first active element and said third resistor.

Claim 14

An auto-reset circuit for generating a power-up reset signal, comprising: a first power-supply terminal for receiving a first potential; a second power-supply terminal for receiving a second potential different from said first potential; an output terminal for output of the reset signal; a first active element having first and second terminals, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal being coupled to said first power-supply terminal, and the second terminal being coupled to the third terminal; a first resistor coupled between the second terminal of said first active element and said second power-supply terminal; a second resistor coupled between said first power-supply terminal and said output terminal; a third resistor coupled to the second terminal of said first active element; a capacitor coupled to said third resistor and said second power-supply terminal, said third resistor and said capacitor thus being coupled in series between the second terminal of said first active element and said second power-supply terminal; and a second active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said second power-supply terminal, the second terminal being coupled to said output terminal, and the third terminal being coupled to a circuit point between said third resistor and said capacitor.

Claim 15

An auto-reset circuit for generating a power-up reset signal, comprising: a first power-supply terminal for receiving a first potential; a second power-supply terminal for receiving a second potential different from said first potential; an output terminal for output of the reset signal; a first active element having first and second terminals, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal being coupled to said first power-supply terminal, and the second terminal being coupled to the third terminal; a first resistor coupled between the second terminal of said first active element and said second power-supply terminal; a second resistor coupled between said first power-supply terminal and said output terminal; a third resistor coupled to the second terminal of said first active element; a capacitor coupled to said third resistor and said second power-supply terminal, said third resistor and said capacitor thus being coupled in series between the second terminal of said first active element and said second power-supply terminal; and a second active element having first and second terminals, and a third terminal for controlling conduction between the first and second terminals, the first terminal being coupled to said second power-supply terminal, the second terminal being coupled to said output terminal, and the third terminal being coupled to a circuit point between said third resistor and said capacitor.

Claim 16

The circuit of claim 11, further comprising a diode via which the third terminal of said second active element is coupled to said first power-supply terminal.

Claim 17

The circuit of claim 11, further comprising: a first control signal input terminal for input of a first control signal to halt current flow during static current measurements; and a third active element having a first terminal, a second terminal, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal and second terminal of which are coupled in series with said first active element between said first power-supply terminal and said first resistor, and the third terminal of which is coupled to said first control signal input terminal.

Claim 18

The circuit of claim 13, further comprising: an inverter coupled to receive and invert the first control signal from said first control signal input terminal; and a logic gate having input terminals coupled to said output terminal and said inverter, for gating said reset signal.

Claim 19

The circuit of claim 13, further comprising: a second control signal input terminal, for input of a second control signal to control output of said reset signal during static current measurements; and a logic gate having input terminals coupled to said output terminal and said second control signal input terminal, for gating said reset signal.

Claim 20

The circuit of claim 13, further comprising a fourth active element having a first terminal, a second terminal, and a third terminal for controlling conduction between the first terminal and second terminal, the first terminal of which is coupled to said second power-supply terminal, the second terminal of which is coupled to the third terminal of said second active element, and the third terminal of which is coupled to said first control signal input terminal, for discharging said capacitor prior to static current measurements.