EP0165855A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Output control circuit for integrated circuit device preventing initial spike noise
Assignee: Fujitsu Ltd
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Filing: 1985-05-29
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Granted: —
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Expires: 2005-05-29
Abstract
Abstract The initial output spike noise which appears when the IC is switched on is suppressed by providing an output control circuit between the output terminal (I) of the inner logic circuit of the IC and the output circuit of the IC. The output control circuit clamps the input terminal of the output circuit until the supply voltage builds up to a steady state. The output control circuit comprises two stages each connected between V CC and ground. The first stage is formed by the series connection of a first FET (N 1 ) and first resistor (R 1 ); the second FET (P i ), a third FET (P 2 ) and a second resistor (R 2 ). The first FET (N 1 ) is controlled by a reset signal (RS) and cuts off the second FET (P 1 ) until the reset signal is released. The second FET cuts off the third FET (P 2 ) which transmits the output signal of the inner circuit to the output circuit (N 2 ) of the IC. When the reset signal is released, the third FET (P 2 ) and, hence, the output circuit (N 2 ) begins to operate normally.
Inventors
- 👤 Fumitaka Asami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 16:31
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
256 words
An output control circuit for an IC (integrated circuit) device clamping the input terminal of the output circuit of said IC to prevent output of initial spike noise which otherwise appears at the starting time when the supply voltage is building up in the IC, characterized by : first and second voltage supply lines for providing said supply voltage; means for receiving a reset signal (RS); a first stage which comprises a first resistive element (R l ) and a first transistor (N 1 , Figs. 2a, 2b ; P 1 , Fig. 3) each connected in series between the first voltage supply line and the second voltage supply line; and a second stage which comprises a second transistor (P 1 , Figs. 2a, 2b; N 1 , Fig. 3), a third transistor (P 2 , Figs. 2a, 2b; N 2 , Fig. 3) and a second resistive element (R 2 ) each connected in series between the first voltage supply line and the second voltage supply line, said first transistor being cut off by the reset signal and controlling the second transistor; said second transistor being cut off under the control of the first transistor until the reset signal is released; said third transistor being controlled by the second transistor and receiving the input signal (I), and transmitting it to the input terminal of said output circuit (N 2 , Fig. 2a; P 3 , N 3 , Fi g. 2b; P 2 , N 3 , Fig. 3), when the reset signal is released.
Claim 2
Dependent Claim
256 words
An output control circuit for an IC (integrated circuit) device clamping the input terminal of the output circuit of said IC to prevent output of initial spike noise which otherwise appears at the starting time when the supply voltage is building up in the IC, characterized by : first and second voltage supply lines for providing said supply voltage; means for receiving a reset signal (RS); a first stage which comprises a first resistive element (R l ) and a first transistor (N 1 , Figs. 2a, 2b ; P 1 , Fig. 3) each connected in series between the first voltage supply line and the second voltage supply line; and a second stage which comprises a second transistor (P 1 , Figs. 2a, 2b; N 1 , Fig. 3), a third transistor (P 2 , Figs. 2a, 2b; N 2 , Fig. 3) and a second resistive element (R 2 ) each connected in series between the first voltage supply line and the second voltage supply line, said first transistor being cut off by the reset signal and controlling the second transistor; said second transistor being cut off under the control of the first transistor until the reset signal is released; said third transistor being controlled by the second transistor and receiving the input signal (I), and transmitting it to the input terminal of said output circuit (N 2 , Fig. 2a; P 3 , N 3 , Fi g. 2b; P 2 , N 3 , Fig. 3), when the reset signal is released.
Claim 3
Dependent Claim
240 words
An output control circuit according to claim 1, characterized in that one end of said first resistive element (R 1 ) is connected to the first voltage supply line; said first transistor (N 1 , Figs. 2a, 2b) is a n-channel FET (field effect transistor) having a source connected to the second voltage supply line, a drain connected to the other end of the first resistive element (R 1 ), and a gate connected to the reset terminal (RS); said second transistor (P 1 , Figs. 2a, 2b) is a p-channel FET having a source connected to the first voltage supply line, a gate connected to the junction point (P) connecting the first resistive element (RI) and the drain of the first transistor; said third transistor (P 2 , Figs. 2a, 2b) is a p-channel FET having a source connected to the drain of the first transistor, a drain connected to one end of the second resistive element (R 2 ), and a gate connected to the output terminal (I) of the inner logic circuit of the IC; another end of the second resistive element (R 2 ) is connected to the second voltage supply line ; and the junction point (Q) of the drain of the second transistor with the second resistive element (R 2 ) is connected to the input terminal of said output circuit (N 2 , Fig. 2a; P 3 , N 3 , Fig. 2b).
Claim 4
Dependent Claim
222 words
An output control circuit according to claim 1, characterized in that : said first transistor (P 1 , Fig. 3) is a p-channel FET having a source connected to the first voltage supply line, a drain connected to one end of the first resistive element (R 1 ), and a gate connected to the reset terminal (RS); another end of said first resistive element is connected to the second voltage supply line; one end of the second resistive element (R 2 ) is connected to the first voltage supply line; said second transistor (N 1 Fig. 3) is a n-channel FET having a source connected to the second voltage supply line, and a gate connected to the junction point (P) connecting the drain of the first transistor to the first resistive element; said third transistor (N 2 , Fig. 3) is a n-channel FET having a source connected to the drain of the first transistor, a drain connected to another end of the second resistive element (R 2 ), and a gate connected to the output terminal of the inner logic circuit of the IC; and the junction point (Q) of the drain of the third transistor with the second resistive element (R 2 ) is connected to the input terminal of said output circuit (P 2 , N 31 Fig. 3).
Claim 5
Dependent Claim
47 words
An output control circuit according to anyone of claims 1 to 3, characterized in that : the resistance of said first and second resistive elements (R 1 , R 2 ) are in a range from a few hundreds ohms to a few hundreds of kilo- ohms.
Claim 6
Dependent Claim
42 words
An output control circuit according to claim 4, characterized in that : at least one of said first and second resistive element is a resistor of which the resistance ranges from a few hundreds ohms to a few hundreds of kilo ohms.
Claim 7
Dependent Claim
47 words
An output control circuit according to claim 4, characterized in that : at least one of said first and second resistive element is a normally on type FET of which the effective inner resistance ranges from a few hundreds ohms to a few hundres of kilo ohms.
Claim 8
Dependent Claim
42 words
An output control circuit according to claim 2, characterized in that : the reset signal is at low level while the supply voltage is in building up phase, and it varies to high level when the supply voltage reaches its specified value.
Claim 9
Dependent Claim
42 words
An output control circuit according to claim 3, characterized in that : the reset signal is at high level while the supply voltage is in building up phase, and it varies to low level when the supply voltage reaches its specified value.
Claim 10
Dependent Claim
49 words
An output control circuit according to anyone of claims 1 to 8, characterized in that : the first voltage supply line is the positive side of the voltage source of the IC; and the second voltage supply line is the negative side of the voltage source of the IC.
References Cited (Backward Citations)
US4019070A
Cited
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