Semiconductor memory device including gate electrode sandwiching a channel region

Claim 2

A semiconductor memory device comprising: an insulated gate transistor including a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between said plurality of main electrode regions, and a gate electrode provided on said channel region with a gate insulator therebetween, said gate electrode having at least two opposing portions that sandwich said channel region therebetween; and an electrically breakable memory element provided on one of said main electrode regions, wherein a doped semiconductor region is provided between said opposing portions beneath said channel region, said doped semiconductor region having a same conductivity type as said channel region and an impurity concentration higher than that of said channel region.

Claim 3

A semiconductor memory device according to claim 1, wherein said memory element has a semiconductor layer, and wherein writing is performed by breaking a junction between said semiconductor layer and another layer adjoining thereto.

Claim 4

A semiconductor memory device according to claim 1, wherein said gate electrode and said doped semiconductor region surround at least four surfaces of said channel region which run parallel to a direction in which carriers are mobilized.

Claim 5

A semiconductor memory device according to claim 3, further comprising a second semiconductor region provided on the surface of said channel which is remote from said high impurity concentration semiconductor region and having the same conductivity type as that of said channel region and a higher impurity concentration than said channel region.

Claim 6

A semiconductor memory device according to claim 1, further comprising a third semiconductor region provided between said main electrode regions and said channel region, said third semiconductor region having the same conductivity type as that of said main electrode regions and a lower impurity concentration than said main electrode regions.

Claim 7

A semiconductor memory device according to claim 1, further comprising an interconnection for a power source which runs parallel to a direction of the source and drain of said transistor.

Claim 8

A semiconductor memory device according to claim 1, wherein an interconnection for a power source is disposed in a direction intersecting a direction of the source and drain of said transistor.

Claim 9

A semiconductor memory device comprising: a plurality of memory cells each of which includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between said plurality of main electrode regions, and a gate electrode provided on said channel region with a gate insulator therebetween, said gate electrode having at least two opposing portions that sandwich said channel region therebetween; and an electrically breakable memory element provided on one of said main electrode regions, wherein a doped semiconductor region is provided between said opposing portions beneath said channel region, said doped semiconductor region having a same conductivity type as said channel region and an impurity concentration higher than that of said channel region, and wherein said plurality of memory cells are matrix connected by a first interconnection which is common to the gate electrodes of said memory cells and a second interconnection which is common to the memory elements of said memory cells, a power source line being disposed between said second interconnections.

Claim 10

A semiconductor memory device comprising: a plurality of memory cells each of which includes: an insulated gate transistor having a plurality of main electrode regions provided along a major surface of a substrate and a channel region provided between said plurality of main electrode regions, and a gate electrode provided on said channel region with a gate insulator therebetween, said gate electrode having at least two opposing portions that sandwich said channel region therebetween; and an electrically breakable memory element provided on one of said main electrode regions, wherein a doped semiconductor region is provided between said opposing portions beneath said channel region, said doped semiconductor region having a same conductivity type as said channel region and an impurity concentration higher than that of said channel region, and wherein said plurality of memory cells are matrix connected by a first interconnection which is common to the gate electrodes of said memory cells and a second interconnection which is common to the memory elements of said memory cells, a power source line being disposed between said second interconnections.

Claim 11

A semiconductor memory device comprising: an insulated gate type transistor including a plurality of main electrode regions and a channel region provided between said plurality of main electrode regions, a gate electrode provided on said channel region with a gate insulator provided therebetween, and a semiconductor region provided in contact with said channel region, said semiconductor region having the same conductivity type as that of said channel region and a higher impurity concentration than said channel region, said gate electrode having at least two opposing portions that sandwich said channel region therebetween, said semiconductor region being provided between said opposing portions and beneath said channel region; and an electrically breakable memory element provided on one of said main electrode regions.

Claim 12

A semiconductor memory device comprising: an insulated gate type transistor including a plurality of main electrode regions and a channel region provided between said plurality of main electrode regions, a gate electrode provided on said channel region with a gate insulator provided therebetween, and a semiconductor region provided in contact with said channel region, said semiconductor region having the same conductivity type as that of said channel region and a higher impurity concentration than said channel region, said gate electrode having at least two opposing portions that sandwich said channel region therebetween, said semiconductor region being provided between said opposing portions and beneath said channel region; and an electrically breakable memory element provided on one of said main electrode regions.

Claim 13

A semiconductor memory device according to claim 9, wherein a plurality of memory cells, including said transistor and said memory element, are provided, said plurality of memory cells being matrix connected to each other by a plurality of first interconnections which are common to the gate electrodes of said plurality of memory cells, and a plurality of second interconnections which are common to the memory elements of said plurality of memory cells, a power source line being disposed between the adjacent second interconnections.

Claim 14

A semiconductor memory device according to claim 1, wherein said gate electrode has an upper region provided on said channel region.