Phase detector for very high frequency clock and data recovery circuits

Claim 2

A phase error detector for use in a data recovery circuit which receives a data signal and a clock signal, comprising: means for receiving a data signal and for receiving a cyclic clock signal that has positive and negative transitions at predefined times in each cycle of said clock signal; a first pulse generator circuit, coupled to said receiving means, which generates a first pulse signal whenever said data signal changes value; said first pulse signal beginning at a time corresponding to said data signal value change and ending at a time corresponding to a predefined one of said transitions of said clock signal; said first pulse signal having a pulse width TW1 that corresponds to the amount of time between said data signal's value change and said predefined one of said transitions of said clock signal; and a second pulse generator circuit, coupled to said receiving means, which generates a second pulse signal whenever said data signal changes value, said second pulse signal having a width TW2 that corresponds to a predefined portion of said clock signal cycle; wherein said first pulse generator circuit and said second pulse generator circuit are substantially identical circuits so that pulse signal generation delays in said first pulse generator circuit are equal to pulse signal generation delays in said second pulse generator circuit; wherein the average pulse width of said first pulse signal is equal to the pulse width of said second pulse signal when there is no phase error between said data signal and said clock signal, and wherein the difference in the pulse widths of said first and said second pulse signals is proportional to the phase error between said data signal and said clock signal.

Claim 3

The phase error detector of claim 1, further including processing means, coupled to said first and second pulse generator circuits, for comparing pulse widths of said first and second pulse signals and generating a phase error signal corresponding to TW1-TW2, the difference between the pulse widths of said first and second pulse signal.

Claim 4

The phase error detector of claim 2, said processing means including first integrating means for integrating a plurality of first pulse signals, second integrating means for integrating a corresponding plurality of second pulse signals, and comparison means coupled to said first and second integrating means, for generating a phase error signal corresponding to the difference between said integrated first and second pulse signals.

Claim 5

The phase error detector of claim 2, said data signal having alternating positive and negative transitions; said processing means including first integrating means for integrating at least two successive ones of first pulse signals, corresponding to successive positive and negative transitions in said data signal; second integrating means for integrating successive ones of second pulse signals corresponding to the first pulse signals integrated by said first integrating means; and comparison means, coupled to said first and second integrating means, for generating a phase error signal corresponding to the difference between said integrated first and second pulse signals.

Claim 6

The phase error detector of claim 1, wherein said second pulse signal is a reference signal which always has a pulse width of about one-half of said clock signal cycle.

Claim 7

A phase error detector for use in a data recovery circuit which receives a data signal and a synthesized clock signal, comprising: a data delay circuit which receives a data signal and generates a first delayed data signal after a propagation delay; a latch circuit which receives a cyclic clock signal that has positive and negative transitions at predefined times in each cycle of said clock signal, said latch circuit including a first sub-circuit that stores said data signal at a predefined time in each cycle of said clock signal, and a second sub-circuit that generates a second delayed data signal corresponding to said stored data signal after a predefined transition in said clock signal; wherein said data delay circuit and said second sub-circuit are identical circuits so that propagation delay of said data signal through said data delay circuit is equal to propagation delay of said stored data signal through said second sub-circuit; and an exclusive-OR circuit, coupled to said data delay and latch circuits, which generates a first pulse signal whenever said first delayed data signal and said second delayed data signal are not equal; said first pulse signal having a width that corresponds to phase error between said data signal and said clock signal.

Claim 8

A phase error detector for use in a data recovery circuit which receives a data signal and a synthesized clock signal, comprising: a data delay circuit which receives a data signal and generates a first delayed data signal after a propagation delay; a latch circuit which receives a cyclic clock signal that has positive and negative transitions at predefined times in each cycle of said clock signal, said latch circuit including a first sub-circuit that stores said data signal at a predefined time in each cycle of said clock signal, and a second sub-circuit that generates a second delayed data signal corresponding to said stored data signal after a predefined transition in said clock signal; wherein said data delay circuit and said second sub-circuit are identical circuits so that propagation delay of said data signal through said data delay circuit is equal to propagation delay of said stored data signal through said second sub-circuit; and an exclusive-OR circuit, coupled to said data delay and latch circuits, which generates a first pulse signal whenever said first delayed data signal and said second delayed data signal are not equal; said first pulse signal having a width that corresponds to phase error between said data signal and said clock signal.

Claim 9

A phase error detector for use in a data recovery circuit which receives a data signal and a synthesized clock signal, comprising: a data delay circuit which receives a data signal and generates a first delayed data signal after a propagation delay; a latch circuit which receives a cyclic clock signal that has positive and negative transitions at predefined times in each cycle of said clock signal, said latch circuit including a first sub-circuit that stores said data signal at a predefined time in each cycle of said clock signal, and a second sub-circuit that generates a second delayed data signal corresponding to said stored data signal after a predefined transition in said clock signal; wherein said data delay circuit and said second sub-circuit are identical circuits so that propagation delay of said data signal through said data delay circuit is equal to propagation delay of said stored data signal through said second sub-circuit; a first exclusive-OR circuit, coupled to said data delay and latch circuits, which generates a first pulse signal whenever said first delayed data signal and said second delayed data signal are not equal; said first pulse signal having a pulse width TW1 that corresponds to phase error between said data signal and said clock signal; and a reference pulse generator coupled to said latch circuit, which receives said clock signal and generates a second pulse signal whenever said data signal changes value, said second pulse signal having a pulse width TW2 that corresponds to a predefined portion of said clock signal cycle; wherein the phase error, if any, between said data signal and said clock signal is proportional to the difference, TW1-TW2, between the pulse widths of the first and second pulse signals.

Claim 10

A phase error detector for use in a data recovery circuit which receives a data signal and a synthesized clock signal, comprising: a data delay circuit which receives a data signal and generates a first delayed data signal after a propagation delay; a latch circuit which receives a cyclic clock signal that has positive and negative transitions at predefined times in each cycle of said clock signal, said latch circuit including a first sub-circuit that stores said data signal at a predefined time in each cycle of said clock signal, and a second sub-circuit that generates a second delayed data signal corresponding to said stored data signal after a predefined transition in said clock signal; wherein said data delay circuit and said second sub-circuit are identical circuits so that propagation delay of said data signal through said data delay circuit is equal to propagation delay of said stored data signal through said second sub-circuit; a first exclusive-OR circuit, coupled to said data delay and latch circuits, which generates a first pulse signal whenever said first delayed data signal and said second delayed data signal are not equal; said first pulse signal having a pulse width TW1 that corresponds to phase error between said data signal and said clock signal; and a reference pulse generator coupled to said latch circuit, which receives said clock signal and generates a second pulse signal whenever said data signal changes value, said second pulse signal having a pulse width TW2 that corresponds to a predefined portion of said clock signal cycle; wherein the phase error, if any, between said data signal and said clock signal is proportional to the difference, TW1-TW2, between the pulse widths of the first and second pulse signals.

Claim 11

The phase error detector of claim 7, further including processing means, coupled to said first exclusive-OR circuit and said reference pulse generator circuit, for comparing pulse widths of said first and second pulse signals and generating a phase error signal corresponding to TW1-TW2, the difference between the pulse widths of said first and second pulse signals.

Claim 12

The phase error detector of claim 8, said processing means including first integrating means for integrating a plurality of first pulse signals, second integrating means for integrating a corresponding plurality of second pulse signals, and comparison means coupled to said first and second integrating means, for generating a phase error signal corresponding to the difference between said integrated first and second pulse signals.

Claim 13

The phase error detector of claim 8, said data signal having alternating positive and negative transitions; said processing means including first integrating means for integrating at least two successive ones of first pulse signals, corresponding to successive positive and negative transitions in said data signal; second integrating means for integrating successive ones of second pulse signals corresponding to the first pulse signals integrated by said first integrating means; and comparison means, coupled to said first and second integrating means, for generating a phase error signal corresponding to the difference between said integrated first and second pulse signals.

Claim 14

The phase error detector of claim 7, wherein said first pulse signal has a pulse width equal to the amount of time between each transition in said data signal and said predefined transition in said clock signal; and the average pulse width of said first pulse signal is equal to the pulse width of said second pulse signal when there is no phase error between said data signal and said clock signal.

Claim 15

The phase error detector of claim 7, wherein said second pulse signal is a reference signal which always has a pulse width of about one-half of said clock signal cycle, and said first pulse signal has an average pulse width that is equal to the pulse width of said second pulse signal when there is no phase error between said data signal and said clock signal.

Claim 16

The phase error detector of claim 7, wherein said reference pulse generator circuit includes: a second latch circuit that regenerates said second delayed data signal with an additional delay of exactly one cycle of said clock signal; a clock delay circuit which receives said clock signal and generates a delayed clock signal after a propagation delay equal to said data delay circuit's propagation delay; and a second exclusive-OR circuit, coupled to said latch circuit and second latch circuit, which receives said clock signal and generates said second pulse signal by regenerating said delayed clock signal whenever said regenerated second delayed data signal and said second delayed data signal are not equal.

Claim 17

The phase error detector of claim 13, wherein said regenerated second delayed data signal and said delayed clock signal comprise a recovered data signal and a recovered clock signal which are synchronized, said recovered clock signal having positive and negative transitions at predefined times in each cycle of said recovered clock signal; each change in value of said recovered data signal being synchronized with a predefined one of said transitions of said recovered clock signal.