Partial-scan built-in self-test technique

Claim 3

The method according to claim 1 wherein the step of shifting the first test vector includes the steps of: reading bits of the first test vector from a first storage register in the integrated circuit; and repetitively clocking the scan chain flip-flops to shift the first test vector therein.

Claim 4

The method according to claim 2 wherein the step of applying the bits of the second test vector comprises the steps of: reading bits of the second test vector from the first storage register; and clocking the non-scan chain flip-flops once.

Claim 5

The method according to claim 1 wherein the compacting step comprises the step of entering response bits from the integrated circuit, and the bits shifted out of the scan flip-flops, into a multiple input shift register within the integrated circuit.

Claim 6

The method according to claim 4 wherein the steps of initializing the integrated circuit comprises the steps of sequentially initializing the first register, the scan chain flip-flops, the non-scan chain flip-flops, and then the second register.

Claim 7

A test system for testing an integrated circuit configured of a plurality of flip-flops, at least one being self-looping and at least a portion of the flip-flops being selected as scan flip-flops and being arranged in a scan chain, to effectuate partial-scan testing of the circuit, comprising: an initializable flip-flop for replacing each self-looping non-scan flip-flop; first register means for storing first and second test vectors for input to the chain of scan flip-flops and for input to the integrated circuit, respectively; controller means coupled to the integrated circuit and to the first register means for: (a) initializing the integrated circuit; (b) causing the first and second test vectors from the first test register to be applied to the chain of scan flip-flops and to the integrated circuit, respectively, during a test interval; and (c) causing the chain of scan flip-flops and the integrated circuit to operate in a non-test (normal) mode following receipt of the first and second test vectors, respectively, so that the integrated circuit generates a response and causes a bit to be shifted into each respective scan chain flip-flop; and means coupled to the integrated circuit for compacting the response generated by the integrated circuit with the bits shifted out of the scan chain flip-flops.

Claim 8

A test system for testing an integrated circuit configured of a plurality of flip-flops, at least one being self-looping and at least a portion of the flip-flops being selected as scan flip-flops and being arranged in a scan chain, to effectuate partial-scan testing of the circuit, comprising: an initializable flip-flop for replacing each self-looping non-scan flip-flop; first register means for storing first and second test vectors for input to the chain of scan flip-flops and for input to the integrated circuit, respectively; controller means coupled to the integrated circuit and to the first register means for: (a) initializing the integrated circuit; (b) causing the first and second test vectors from the first test register to be applied to the chain of scan flip-flops and to the integrated circuit, respectively, during a test interval; and (c) causing the chain of scan flip-flops and the integrated circuit to operate in a non-test (normal) mode following receipt of the first and second test vectors, respectively, so that the integrated circuit generates a response and causes a bit to be shifted into each respective scan chain flip-flop; and means coupled to the integrated circuit for compacting the response generated by the integrated circuit with the bits shifted out of the scan chain flip-flops.

Claim 9

The apparatus according to claim 6 wherein the controller means comprises: a clock control circuit for clocking the chain of integrated circuits and for clocking the non-scan flip-flops; a finite state machine for controlling the operation of the first register means, the scan chain flip-flops and the integrated circuit at preselected intervals; and a plurality of counters coupled to the finite state machine for signaling the occurrence each preselected interval.

Claim 10

The invention according to claim 6 wherein the first register comprises a linear feedback shift register.

Claim 11

The invention according to claim 6 wherein said means for compacting comprises a multiple input shift register.

Claim 12

The method according to claim 6 wherein each initializable flip-flop comprises: a D-type flip-flop having an input and an output; and a multiplexer for selectively supplying an initializing signal and normal data to the input of the D-type flip-flop.

Claim 13

The apparatus according to claim 6 wherein the controller is responsive to control signals from an external boundary scan test system.