Test chip for semiconductor fault analysis

Claim 2

A semiconductor test chip for use in semiconductor fabrication fault analysis of CMOS Integrated Circuits, characterized in that it comprises an n×m array of transmission gate cells arranged such that within a given row respective strips of conductive material of a first type form common source and drain electrodes for the transistors of the row, the sources and drain of each row being independent, and within a column strips of conductive material of a second type form common gate electrodes such that each column of transistors can be turned on independently; input means for selectively applying a predetermined binary bit pattern to inputs of the rows of transmission gate cells, multiplexer means including output transmission gates connected to respective outputs of the rows of said array for selectively addressing the output of each row of transmission gate cells; means for selectively turning on each column of transmission gate cells; a center-pulled operational amplifier connected to the outputs of said output transmission gate cells; and means for coding the output of said operational amplifier according a three-level logic scheme having logic states 0, 1, X, where 0 represents an output voltage in a first predetermined range, X represents an output voltage in a second predetermined range, and 1 represents an output voltage in a third predetermined range.

Claim 3

A semiconductor test chip as claimed in claim 1, characterized in that said first type of material is metal and said second type of material is polycrystalline silicon.

Claim 4

A semiconductor test chip as claimed in claim 2, characterized in that said scheme is such that the cells are probed by applying to the inputs of all the rows, said row inputs being connected to the sources of all the cells in the row, a logic 0 and 1 according to the following scheme: ______________________________________ Row Bit Patterns ______________________________________ n-1 0 1 0 1 n 0 0 1 1 n+1 0 1 0 1 ______________________________________

Claim 5

A semiconductor test chip as claimed in claim 3, arranged such that the cells are probed first by turning off all transmission gate cells (HI-Z) and probing all rows by sequentially applying normal bit patterns thereto and sensing the tri-level outputs, and second by selectively turning on each column and again sensing the tri-level outputs.

Claim 6

A semiconductor test chip as claimed in claim 1, characterized in that said output is coded according to a tri-level logic scheme, a first level corresponding to a low voltage range, a second level corresponding to an intermediate voltage range, and a third level corresponding to a high voltage range, and the physical nature and location of defects in the chip are determined from the tri-level codes appearing at the outputs of each row when the predetermined bit patterns are applied to the row inputs.

Claim 7

A semiconductor test chip as claimed in claim 1, characterized in that said input means comprises an exclusive OR gate array.

Claim 8

A semiconductor test chip as claimed in claim 1, characterized in that said input means comprises an exclusive NOR gate array.

Claim 9

A semiconductor test chip as claimed in claim 1, characterized in that said input means comprises a shift register.

Claim 10

A semiconductor test chip as claimed in claim 1, characterized in that said input means comprises a multiplexer.

Claim 11

A semiconductor test chip as claimed in claim 1, characterized in that said output means comprises a shift register.

Claim 12

A semiconductor test chip as claimed in claim 1, characterized in that said means for selectively turning on each column of transmission gate cells comprises a shift register.

Claim 13

A semiconductor test chip as claimed in claim 1, comprising a 128×256 array of cells with twelve I/O pads located on the chip.

Claim 14

A semiconductor test chip as claimed in claim 1, characterized in that said operational amplifier is located off the chip.

Claim 15

A semiconductor test chip as claimed in claim 1 wherein method of evaluating the performance of a semiconductor fabrication process for making CMOS Integrated Circuits, comprises fabricating said test chip said process, applying said predetermined bit patterns to said row inputs, sensing the tri-level codes at the row outputs for the predetermined bit patterns applied to the row inputs at Hi-Z, i.e. with all transmission gates off, and with the columns of cells selectively turned ON, and determining from the tri-level coded outputs the physical nature and location of the defects in the chip.

Claim 16

A method as claimed in claim 14, characterized in that said scheme is such that the cells are probed by applying to the inputs of all the rows, said row inputs being connected to the sources of all the cells in the row, a logic 0 and 1 according to the following scheme: ______________________________________ Row Bit Patterns ______________________________________ n-1 0 1 0 1 n 0 0 1 1 n+1 0 1 0 1 ______________________________________

Claim 17

A method as claimed in claim 15, characterized in that the cells are probed first by turning off all transmission gate cells (HI-Z) and probing all rows and sensing the tri-level outputs, and second by selectively turning on each column and again sensing the tri-level outputs.

Claim 18

A method as claimed in claim 14, characterized in that the faults are determined from the tri-level coded outputs as follows: __________________________________________________________________________ Defect HI-Z possible HI-Z Y-dir Local X-dir Y-dir XY __________________________________________________________________________ DsN 0000 00XX 00XX X DsP 1111 XX11 XX11 X GSN XX0X* XX0X* XX11 00XX XX11 + XY GSP X1XX* X1XX* 00XX XX11 XY GDN 0000 00XX XX11 XY GDP 1111 XX11 00XX XY GG 0011 0011 XY DS 0011 Y S.sub.n D.sub.n-1 0011 0XX1 0XX1 Y GOP 00XX Y GON XX11 Y S.sub.n S.sub.n-1 O XXXX XXXX + XY SSO XX11 XXXX* XY DDO 00XX XXXX - XY D.sub.n D.sub.n+1 O XXXX XXXX - XY SsN 00XX 00XX Y Ssp XX11 XX11 Y GsN XX11 XX11 + X* GsP 00XX 00XX + X* DON XX11 XY DOP 00XX XY __________________________________________________________________________ where the codes have the following meanings: ______________________________________ 0: logic zero 1: logic one X: intermediate level within defined limits DsN: drain substrate short DsP: GSN: gate source short GSP: GDN: GDP: GG: gate n-gate p short DS: drain-source short S.sub.n D.sub.n-1 : short of the drain to the source of the transistor below (Metal-Metal) GOP: gate open GON: S.sub.n-1 S.sub.n O: source open between cells of the same row SSO: source open between transistors of the same cell DDO: D.sub.n D.sub.n+1 O: SsN: source-substrate short Ssp: GsN: GsP: DON: drain open N channel, note: SON is the same DOP: ______________________________________ HI-Z represents the code seen at the output of the probed row in the high impedance state as the 0011 bit pattern is applied to its input, The HI-Z Y dir column shows those defects that cause the error to propagate from the row containing the defective cell to the bottom of the array; The Local column shows the sensed output pattern for all rows when a defective cell of a probed row is selected; The X dir column shows the code seen on the defective row as the columns are selected in turn; +means from defect position to far right, -from far left to defect position; The Y dir column shows the code seen in the defective column as the output rows are scanned in turn; +means from the defect to the bottom of the array, -means from the top of the array to the row containing the defective cell; The X-Y Possible column indicates the coordinates that can be identified from the output codes; a * means the identification is not straight forward for the missing direction but can be calculated approximately.