Semiconductor integrated circuit device equipped with substrate biasing system selectively powered from internal and external power sources

Claim 2

A semiconductor integrated circuit device fabricated on a semiconductor substrate, comprising: a) an internal circuit; b) a power supply system having a means for distributing an external power voltage supplied from the outside of said semiconductor integrated circuit device, and an internal step-down circuit operative to produce an internal power voltage from said external power voltage and to regulate said internal power voltage to a predetermined reference level internally produced; and c) a substrate bias system operative to bias said semiconductor substrate to a certain level with a bias voltage, and having a first bias voltage producing circuit for producing said bias voltage from said external power voltage and a second bias voltage producing circuit for producing said bias voltage from said internal power voltage, and first bias voltage producing circuit being activated before said internal power voltage level reaches said predetermined reference level.

Claim 3

A semiconductor integrated circuit device as set forth in claim 1, in which said substrate bias system further has a power-on detecting circuit for producing a detecting signal when said internal power voltage level reaches said predetermined reference level, and a voltage monitoring circuit operative to monitor a voltage level of said semiconductor substrate for supplying a control signal indicative of a difference from said certain level for activating said first bias voltage producing circuit.

Claim 4

A semiconductor integrated circuit device as set forth in claim 2, in which said voltage monitoring circuit comprises a first voltage divider coupled between a reference voltage line for said predetermined reference voltage and said semiconductor substrate and activated with a first complementary signal for producing a quasi substrate voltage signal, a second voltage divider coupled between said reference voltage line and a constant voltage line and activated with an enable signal at an active level complementary to said first complementary signal for producing a constant voltage signal, an activation circuit responsive to said detecting signal and a second complementary signal of said control signal having an active level for producing said enable signal and said first complementary signal, and a voltage comparing circuit activated with said first complementary signal and operative to compare said quasi substrate voltage signal with said constant voltage signal for producing said control signal and said second complementary signal, said enable signal and said second complementary signal being kept in said active levels while said internal power voltage rises toward said predetermined reference level.

Claim 5

A semiconductor integrated circuit as set forth in claim 3, in which said first and second voltage dividers have a series combination of a first enhancement type switching transistor of a first channel conductivity type and a plurality of first resistors, and a series combination of a second enhancement type switching transistor of a second channel conductivity type opposite to said first channel conductivity type and a plurality of second resistors, respectively.

Claim 6

A semiconductor integrated circuit device as set forth in claim 3, in which said activation circuit comprises a NOR gate supplied with said detecting signal and said second complementary signal for producing said enable signal, and a first inverter coupled with an output node of said NOR gate for producing said first complementary signal.

Claim 7

A semiconductor integrated circuit device as set forth in claim 3, in which said voltage comparing circuit comprises a voltage comparator activated with said first complementary signal and operative to compare said quasi substrate voltage signal with said constant voltage signal, and a series combination of inverters coupled with an output node of said voltage comparator for producing said second complementary signal and said control signal.

Claim 8

A semiconductor integrated circuit device as set forth in claim 2, in which said voltage monitoring circuit comprises a first voltage divider coupled between a reference signal line for said predetermined reference voltage level and said semiconductor substrate for producing a quasi substrate voltage signal, a second voltage divider coupled between said reference voltage line and a constant voltage line for producing a constant voltage signal, a current mirror circuit responsive to difference between said quasi substrate voltage signal and said constant voltage signal for producing an output voltage signal, and an output circuit supplied with said output voltage signal for producing said control signal.

Claim 9

A semiconductor integrated circuit device as set forth in claim 7, in which said first and second voltage dividers have a plurality of first resistors coupled in series and a plurality of second resistors coupled in series, respectively.

Claim 10

A semiconductor integrated circuit device as set forth in claim 7, in which said first voltage divider has a first enhancement type switching transistor of a first channel conductivity type and a plurality of first resistors coupled in series between said first enhancement type switching transistor and said semiconductor substrate, and said second voltage divider has a second enhancement type switching transistor of said first channel conductivity type and a plurality of second resistors coupled in series between said second enhancement type switching transistor and said constant voltage line, said first and second enhancement type switching transistors turning on with a first enable signal before said internal power voltage level reaches said predetermined reference level.

Claim 11

A semiconductor integrated circuit device as set forth in claim 9, in which said current mirror circuit comprises a series combination of a first enhancement type load transistor of said first channel conductivity type and a first enhancement type amplifying transistor of a second channel conductivity type opposite to said first channel conductivity type coupled between a power voltage line of said external power voltage and a common node, a series combination of a second enhancement type load transistor of said first channel conductivity type and a second enhancement type amplifying transistor of said second channel conductivity type coupled between said power voltage line of said external power voltage and said common node, and a third enhancement type switching transistor coupled between said common node and said constant voltage line, said first and second enhancement type amplifying transistors having respective gate electrodes respectively coupled with a monitoring node of said first voltage divider provided between said plurality of first resistors and with a constant voltage node of said second voltage divider provided between said plurality of second resistors, said third enhancement type switching transistor having a gate electrode supplied with a second enable signal turning on with a second enable signal before said internal power voltage level reaches said predetermined reference level.

Claim 12

A semiconductor integrated circuit device as set forth in claim 10, in which said first resistors and said second resistors have respective resistances regulated in such a manner that said monitoring node becomes equal in voltage level to said constant voltage node when bias voltage level of said semiconductor substrate is equalized to said constant voltage line.

Claim 13

A semiconductor integrated circuit device as set forth in claim 1, in which said semiconductor integrated circuit device is a dynamic random access memory device.