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US5328860A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device

Assignee: Samsung Electronics Co Ltd
•
Filing: 1993-04-15
•
Granted: 1994-07-12
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Expires: 2013-04-15
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Abstract

Abstract A method for manufacturing BiCMOS semiconductor devices in which an oxide layer formed on the surface of a semiconductor substrate for the purpose of facilitating formation of spacers adjacent to sidewalls of the gates of the MOS transistors thereof is only partially removed, by using a dry etching process, to thereby leave a residual oxide layer, which is then removed, by using a wet etching process, to thereby form the spacers. Alternatively, all portions of the oxide layer except a portion thereof overlying the base-emitter region of the bipolar transistor of the BiCMOS device is removed, thereby precluding the necessity of etching the oxide layer away at the base-emitter junction. In either case, the DC forward current gain Hfe and linearity of the bipolar transistor of the BiCMOS device are enhanced.

Inventors

  • 👤 Yong J. Lee
  • 👤 Duk M. Yi
  • 👤 Young O. Kim
  • 👤 Gyu C. Kim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 17:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/009

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 103 words
A method for forming spacers adjacent to sidewalls of a gate electrode of a first MOS transistor formed in a semiconductor well region of a first conductivity type formed in a semiconductor substrate of a second conductivity type, comprising the steps of: forming an oxide layer over said gate and said semiconductor well region; partially removing said oxide layer by using a dry etching process, to thereby leave a residual oxide layer over said gate and said semiconductor well region; and, removing said residual oxide layer by using a wet etching process, to thereby form spacers adjacent to said sidewalls of said gate.
Claim 2
Independent Claim 103 words
A method for forming spacers adjacent to sidewalls of a gate electrode of a first MOS transistor formed in a semiconductor well region of a first conductivity type formed in a semiconductor substrate of a second conductivity type, comprising the steps of: forming an oxide layer over said gate and said semiconductor well region; partially removing said oxide layer by using a dry etching process, to thereby leave a residual oxide layer over said gate and said semiconductor well region; and, removing said residual oxide layer by using a wet etching process, to thereby form spacers adjacent to said sidewalls of said gate.
Claim 3
Dependent Claim 41 words
The method as set forth in claim 1, wherein said semiconductor substrate further includes a bipolar transistor and a second MOS transistor having a conductivity type opposite that of said first MOS transistor formed therein, to thereby provide a BiCMOS device.
Claim 4
Dependent Claim 19 words
The method as set forth in claim 1, wherein said dry etching process comprises a reactive ion etching process.
Claim 5
Dependent Claim 19 words
The method as set forth in claim 1, wherein said oxide layer has a thickness of approximately 2000-3000 angstroms.
Claim 6
Dependent Claim 20 words
The method as set forth in claim 4, wherein said residual oxide layer has a thickness of approximately 200-500 angstroms.

References Cited (Backward Citations)

JPS6089926A Cited
US4690728A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-07-11 1998-01-10 1998-07-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-07-11 2002-01-10 2002-07-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-07-11 2006-01-10 2006-07-12 $7700.00 Window Closed / Lapsed

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