Disabled memory sections for degraded operation of a vector supercomputer

Claim 3

The method according to claim 1 wherein the failed shared memory portion is defined as one half of the shared memory, and the failure free shared memory portion is defined as the other half of the shared memory.

Claim 4

The method according to claim 2 wherein the two halves of memory are divided in terms of upper memory and lower memory.

Claim 5

The method according to claim 1, wherein an address is comprised of at least thirty two address bits 2 0 -2 31 , and wherein each of the address bits has a corresponding value, wherein the translating (f) further comprises the steps of: (a) shifting address bits 2 21 through 2 31 up one address bit; (b) moving the value of bit 2 2 into bit 2 21 ; and (c) forcing the value of bit 2 2 to a logical high value if the failed memory portion is contained in a first portion of memory, or to a logical low value if the failed memory portion is contained in a second portion of memory.

Claim 6

The method according to claim 1, wherein an address is comprised of n address bits 2 0 -2 n , including address bits 2 x and 2 y , and wherein each address bit has a corresponding value, wherein the translating step (f) further comprises the steps of: (a) shifting address bits 2 x through 2 n up one address bit; (b) moving the value of address bit 2 y into address bit 2 x ; and (c) forcing the value of bit 2 y to a first value if the failed memory portion is contained in a first portion of memory, or to a second value if the failed memory portion is contained in a second portion of memory.

Claim 7

A multiprocessing computer system for simultaneously running operating programs and diagnostic programs, comprising; memory means including multiple sections of memory having interleaved addresses for storing data at specified memory reference addresses within a contiguous address space across all of said sections; processor means including a plurality of processors for executing instructions and for storing said data in said memory means; failure detection means connected to said memory means and said processor means for detecting a hardware failure in said memory means; and address translation means operable in response to said failure detection means for translating said memory reference addresses to a first portion of said memory means into memory reference addresses to a second portion of said memory means.

Claim 8

A multiprocessing computer system for simultaneously running operating programs and diagnostic programs, comprising; memory means including multiple sections of memory having interleaved addresses for storing data at specified memory reference addresses within a contiguous address space across all of said sections; processor means including a plurality of processors for executing instructions and for storing said data in said memory means; failure detection means connected to said memory means and said processor means for detecting a hardware failure in said memory means; and address translation means operable in response to said failure detection means for translating said memory reference addresses to a first portion of said memory means into memory reference addresses to a second portion of said memory means.

Claim 9

The multiprocessing computing system according to claim 6 further including a maintenance workstation through which an operator may control said address translation means to translate 1) all memory reference addresses sent from at least one of said plurality of processors to all of said sections of memory into 2) memory reference addresses sent only to a subset of all of said sections of memory of said memory means such that the memory address space remains contiguous.

Claim 10

The multiprocessing computer system according to claim 6 wherein said address translation means further includes means for forcing at least one of the address bits of said memory reference address which corresponds to said first portion of said memory means to a value which corresponds to said second portion of said memory means.

Claim 11

The multiprocessing computer system according to claim 8 wherein said address translation means further includes shift logic means for shifting at least a portion of the address bits of said memory reference address which correspond to said contiguous address space across all of said sections of said memory means to cause the address bits of said memory reference address to correspond to a contiguous address space across a portion of said sections of said memory means.

Claim 12

The multiprocessing computing system according to claim 9 wherein said first portion of said memory means and said second portion of said memory means each comprise one half of said memory means.

Claim 13

A multiprocessing computer system for simultaneously running operating programs and diagnostic programs, comprising; memory means including multiple sections of memory having interleaved addresses for storing data at specified memory reference addresses within a contiguous address space across all of said sections; processor means including a plurality of central processors for executing instructions and for storing said data in said memory means; address control means for outputting said memory reference addresses; and maintenance workstation means through which an operator may control said address control means to force at least one of the address bits of all of said memory reference addresses from a selected central processor to a fixed value to force said selected central processor to access only a selected portion of all of said sections of said memory means.

Claim 14

A multiprocessing computer system for simultaneously running operating programs and diagnostic programs, comprising; memory means including multiple sections of memory having interleaved addresses for storing data at specified memory reference addresses within a contiguous address space across all of said sections; processor means including a plurality of central processors for executing instructions and for storing said data in said memory means; address control means for outputting said memory reference addresses; and maintenance workstation means through which an operator may control said address control means to force at least one of the address bits of all of said memory reference addresses from a selected central processor to a fixed value to force said selected central processor to access only a selected portion of all of said sections of said memory means.

Claim 15

The multiprocessing computer system according to claim 11 further including: I/O means including a plurality of I/O processors for interfacing between peripherals and said memory means and for storing said data in said memory means, each of said I/O processors being associated with one of said central processors; said address control means further including a plurality of first ports between each of said central processors of said processor means and said memory means, further including a plurality of second ports between each of said I/O processors of said I/O means and said memory means; said address control means further operable in response to said maintenance workstation means for forcing at least one of the address bits of all of said memory reference addresses from a selected central processor through a selected first port to a fixed value thereby forcing said selected central processor to access only a selected portion of all of said sections of said memory means; and said address control means further operable in response to said maintenance workstation means for simultaneously not forcing any of the address bits of all of said memory reference addresses from a selected I/O processor through a selected second port to a fixed value thereby allowing said selected I/O processor to access all of said sections of said memory means.

Claim 16

The multiprocessing computer system according to claim 11 further including: I/O means including a plurality of I/O processors for interfacing between peripherals and said memory means and for storing said data in said memory means, each of said I/O processors being associated with one of said central processors; said address control means further including a plurality of first ports between each of said central processors of said processor means and said memory means, further including a plurality of second ports between each of said I/O processors of said I/O means and said memory means; said address control means further operable in response to said maintenance workstation means for forcing at least one of the address bits of all of said memory reference addresses from a selected central processor through a selected first port to a fixed value thereby forcing said selected central processor to access only a selected portion of all of said sections of said memory means; and said address control means further operable in response to said maintenance workstation means for simultaneously forcing at least one of the address bits of all of said memory reference addresses from a selected I/O processor through a selected second port to a fixed value thereby forcing said selected I/O processor to access only a selected portion of all of said sections of said memory means.