Circuit arrangement for bit rate adaptation

Claim 1

A circuit arrangement for converting the bit rate of a frame structured input signal to a predetermined nominal bit rate, each frame of said input signal including data bits and auxiliary bits; said circuit arrangement comprising: an elastic store for receiving and storing data bits of the input signal; a write address counter for writing data bits of said input signal into said elastic store at the bit rate of said signal, keeping count of the data bits written therein; a read address counter for reading-out the stored data bits and keeping count thereof, read-out being at a bit rate in accordance with a read clock supplied to said read address counter; a phase comparator for determining the distance between the counts of said write address counter and said read address counter, and producing a control error signal corresponding to such distance; a control circuit responsive to said control error signal to produce a frequency control signal; a transformation circuit for transforming the frequency control signal into a pulse sequence with variable frequency; and a read clock generating circuit for supplying said read clock to said read address counter substantially at said predetermined nominal bit rate, said read-clock generating circuit comprising an oscillator for receiving said pulse sequence and being controlled thereby to vary the bit rate of the read clock relative to said predetermined nominal bit rate in accordance with said pulse sequence; and said phase comparator, control circuit, read clock generating circuit and write address circuit constituting a control loop whereby the bit rate of the read clock is controlled so as to rapidly restore the distance between the counts of said write address counter and said read address counter to a desired value in the event of abrupt departures from such desired value due to abrupt changes in the bit rate of said input signal.