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US5327385A
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Method of erasure for a non-volatile semiconductor memory device
Assignee: NEC Electronics Corp
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Filing: 1993-02-19
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Granted: 1994-07-05
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Expires: 2013-02-19
Abstract
Abstract The invention provides a method of erasure for a non-volatile semiconductor memory device having a floating gate. For a first time interval, a voltage having one polarity is applied to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of electrons from said floating gate through a tunneling oxide film. For a second time interval after said first time interval, a voltage having an opposite polarity to said one polarity is applied to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of electrons from a channel region of said memory device to said floating gate through said tunneling oxide film.
Inventors
- 👤 Kenichi Oyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:09
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3409; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
153 words
A method of erasure for a non-volatile semiconductor memory device having a floating gate, said method comprising the steps of: applying a first voltage having one polarity to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of carriers from said floating gate through a tunneling oxide film; and applying a second voltage having an opposite polarity to said one polarity to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of carriers from a channel region of said memory device to said floating gate through said tunneling oxide film; wherein a voltage level of said first voltage application has the same absolute value as a voltage level of said second voltage application.
Claim 2
Independent Claim
153 words
A method of erasure for a non-volatile semiconductor memory device having a floating gate, said method comprising the steps of: applying a first voltage having one polarity to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of carriers from said floating gate through a tunneling oxide film; and applying a second voltage having an opposite polarity to said one polarity to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of carriers from a channel region of said memory device to said floating gate through said tunneling oxide film; wherein a voltage level of said first voltage application has the same absolute value as a voltage level of said second voltage application.
Claim 3
Dependent Claim
23 words
The method of erasure as claimed in claim 1, wherein said second voltage application follows said first voltage application through a time interval.
Claim 4
Dependent Claim
39 words
The method of erasure as claimed in claim 1, further comprising the step of applying a third voltage having an opposite polarity to said voltage polarity of said second voltage application to a substrate during said second voltage application.
Claim 5
Dependent Claim
17 words
The method of erasure as claimed in claim 1, wherein said carriers exhibiting said tunneling comprise electrons.
Claim 6
Dependent Claim
21 words
The method of erasure as claimed in claim 1, wherein said erasure accomplished by said first voltage application is an over-erasure.
Claim 7
Independent Claim
155 words
A method of erasure for a non-volatile semiconductor memory device having a floating gate, said method comprising the steps of: applying a first voltage having one polarity to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of carriers from said floating gate through a tunneling oxide film; applying a second voltage having an opposite polarity to said one polarity to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of carriers from a channel region of said memory device to said floating gate through said tunneling oxide film; and applying a third voltage having an opposite polarity to said voltage polarity of said second voltage application to a substrate during said second voltage application.
Claim 8
Independent Claim
155 words
A method of erasure for a non-volatile semiconductor memory device having a floating gate, said method comprising the steps of: applying a first voltage having one polarity to a control gate of said memory device under a bias application between source and drain regions so as to accomplish an erasure by a tunneling of carriers from said floating gate through a tunneling oxide film; applying a second voltage having an opposite polarity to said one polarity to said control gate of said memory device without bias application between said source and drain regions so as to accomplish a convergence of a threshold voltage into a voltage level by a tunneling of carriers from a channel region of said memory device to said floating gate through said tunneling oxide film; and applying a third voltage having an opposite polarity to said voltage polarity of said second voltage application to a substrate during said second voltage application.
Claim 9
Dependent Claim
23 words
The method of erasure as claimed in claim 6, wherein said second voltage application follows said first voltage application through a time interval.
Claim 10
Dependent Claim
32 words
The method of erasure as claimed in claim 6, wherein a voltage level of said first voltage application has the same absolute value as a voltage level of said second voltage application.
Claim 11
Dependent Claim
17 words
The method of erasure as claimed in claim 6, wherein said carriers exhibiting said tunneling comprise electrons.
Claim 12
Dependent Claim
21 words
The method of erasure as claimed in claim 6, wherein said erasure accomplished by said first voltage application is an over-erasure.
References Cited (Backward Citations)
US5233562A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |