Patent US3056723A successfully refreshed from Google Patents.
Patent US5327172A successfully refreshed from Google Patents.
US5327172A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polling for detection of power supply or other failures of a digital circuit
Assignee: Vantiva SA
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Filing: 1992-04-23
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Granted: 1994-07-05
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Expires: 2012-04-23
Abstract
Abstract A television receiver includes a standby power supply, and an operational or run mode power supply. A microprocessor coupled to the standby power supply controls switching between a run mode, where the standby and run mode power supplies are operative, and a standby mode where only the standby supply is operative. The switching is normally made in response to switch inputs or in response to a signal from a remote controller. The microprocessor is in digital communication with a digital circuit, such as a phase locking tuner, over a bidirectional data bus. The microprocessor is programmed to poll the digital circuit periodically and to monitor the data on the data bus for an expected response to a poll. When the digital circuit fails to respond to the poll, or responds inappropriately, as may occur with lack of adequate power to the digital circuit from the run power supply, the microprocessor automatically switches into the standby mode and disables the run supply. The microprocessor switches back into the run mode upon command, unless data stored in memory indicates a recent or repeated automatic change into the standby mode after a detected failure.
Inventors
- 👤 Siew M. Tan
- 👤 Chon S. Oh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2015; H; H04; H04N; H04N17/00; H04N5/00; H04N5/63; H02; H02M; H02M1/00; H02M1/0003; H02M1/0032; Y; Y02; Y02B; Y02B70/00; Y02B70/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
187 words
An apparatus comprising: a digital circuit coupled to a power supply, said power supply providing power to a plurality of loads inclusive of said digital circuit; a data bus coupled to said digital circuit and operable to communicate data bidirectionally via said data bus; and a digital processor coupled to said power supply and to said data bus for supplying to said digital circuit, via said data bus, during a normal operating condition, a first plurality of digital command signals to cause said digital circuit to assume various normal operating modes, said digital circuit supplying on said data bus, during said normal operating condition, a second plurality of digital signals indicative of said various normal operating modes for monitoring by said digital processor to generate in response thereto said first plurality of digital command signals, wherein upon the occurrence of a failure operating condition, said digital circuit is incapable of supplying on said data bus any one of said second plurality of digital signals, and in the absence of any one of said second plurality of digital signals, said digital processor enters a protective mode of operation.
Claim 2
Independent Claim
187 words
An apparatus comprising: a digital circuit coupled to a power supply, said power supply providing power to a plurality of loads inclusive of said digital circuit; a data bus coupled to said digital circuit and operable to communicate data bidirectionally via said data bus; and a digital processor coupled to said power supply and to said data bus for supplying to said digital circuit, via said data bus, during a normal operating condition, a first plurality of digital command signals to cause said digital circuit to assume various normal operating modes, said digital circuit supplying on said data bus, during said normal operating condition, a second plurality of digital signals indicative of said various normal operating modes for monitoring by said digital processor to generate in response thereto said first plurality of digital command signals, wherein upon the occurrence of a failure operating condition, said digital circuit is incapable of supplying on said data bus any one of said second plurality of digital signals, and in the absence of any one of said second plurality of digital signals, said digital processor enters a protective mode of operation.
Claim 3
Dependent Claim
25 words
An apparatus according to claim 1, wherein the digital circuit is a tuner coupled to the data bus for bidirectional communications with the digital processor.
Claim 4
Dependent Claim
56 words
An apparatus according to claim 2, wherein the digital processor is operable to periodically poll the tuner over the data bus and the tuner is operable to reply to a poll by transmitting a status indication on the data bus, said failure condition being detected upon failure of the tuner to respond to the poll correctly.
Claim 5
Dependent Claim
26 words
An apparatus according to claim 3, wherein the failure condition is detected by lack of a response from the tuner for at least two successive polls.
Claim 6
Dependent Claim
41 words
An apparatus according to claim 1, wherein said power supply comprises a run power supply and a standby power supply, said digital circuit being coupled to the run power supply and the digital processor being coupled to the standby power supply.
Claim 7
Independent Claim
209 words
An apparatus comprising: a least two digital circuits coupled to a power supply, said power supply providing power to a plurality of loads inclusive of said digital circuits; a data bus coupled to said digital circuits and operable to communicate data bidirectionally via said data bus; and a digital processor coupled to said data bus for communication with said digital circuits, and having means to control said digital circuits and at least another one of said plurality of loads according to a plurality of operating modes including a protective operating mode; said digital processor being programmed to communicate sequentially with said digital circuits and monitor data on said data bus to verify data from each digital circuit to detect a failure condition, and upon detecting a failure of one digital circuit, said digital processor continues to communicate with the other digital circuit to verify the response therefrom, a detected failure of said one digital circuit being stored in a memory for identifying the failed digital circuit, and upon failure detection of the other digital circuit, said digital processor being programmed to identify said power supply as having failed and store such a failure identification in said memory, and having stored said failure identification, to assume said protective operating mode.
Claim 8
Independent Claim
209 words
An apparatus comprising: a least two digital circuits coupled to a power supply, said power supply providing power to a plurality of loads inclusive of said digital circuits; a data bus coupled to said digital circuits and operable to communicate data bidirectionally via said data bus; and a digital processor coupled to said data bus for communication with said digital circuits, and having means to control said digital circuits and at least another one of said plurality of loads according to a plurality of operating modes including a protective operating mode; said digital processor being programmed to communicate sequentially with said digital circuits and monitor data on said data bus to verify data from each digital circuit to detect a failure condition, and upon detecting a failure of one digital circuit, said digital processor continues to communicate with the other digital circuit to verify the response therefrom, a detected failure of said one digital circuit being stored in a memory for identifying the failed digital circuit, and upon failure detection of the other digital circuit, said digital processor being programmed to identify said power supply as having failed and store such a failure identification in said memory, and having stored said failure identification, to assume said protective operating mode.
Claim 9
Independent Claim
150 words
An apparatus comprising: a power supply having a run power supply and a standby power supply; a digital circuit coupled to said run power supply; a data bus coupled to said digital circuit and operable to communicate data bidirectionally via said data bus; and a digital processor coupled to said standby power supply and coupled to said data bus for communication with said digital circuit, said digital processor having a plurality of operating modes including a protective operating mode, and having means to control said digital circuit and at least one other load powered by said power supply, said digital processor being programmed to monitor data on said data bus and to verify data from said digital circuit, wherein upon failure of said run power supply, said digital circuit fails to provide data to said data bus, and said digital processor detects said failure and assumes said protective operating mode.
Claim 10
Independent Claim
150 words
An apparatus comprising: a power supply having a run power supply and a standby power supply; a digital circuit coupled to said run power supply; a data bus coupled to said digital circuit and operable to communicate data bidirectionally via said data bus; and a digital processor coupled to said standby power supply and coupled to said data bus for communication with said digital circuit, said digital processor having a plurality of operating modes including a protective operating mode, and having means to control said digital circuit and at least one other load powered by said power supply, said digital processor being programmed to monitor data on said data bus and to verify data from said digital circuit, wherein upon failure of said run power supply, said digital circuit fails to provide data to said data bus, and said digital processor detects said failure and assumes said protective operating mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |