US5327103A
Expired / Lapsed
US
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Lock detection circuit for a phase lock loop
Assignee: Apple Inc
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Filing: 1993-06-29
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Granted: 1994-07-05
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Expires: 2013-06-29
Abstract
Abstract A lock detection circuit (2) for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal (REFERENCE). The lock detection circuit includes a circuit for generating first (UP) and second (DOWN) pulses, the first and second pulses respectively representing positive and negative differences between a parameter, such as phase, of the PLL signal and a parameter of the reference signal, and a first counter (4) for counting sets of first and second, pulses, each set comprising a first pulse followed by a second pulse, the first counter on counting a predetermined number of sets of pulses providing a first count complete signal. The lock detection circuit further includes a second counter (6) for counting transitions of the reference signal (REFERENCE), and being coupled to the circuit for generating whereby the second counter is reset by the first (UP) or second (DOWN)pulse, the second counter (6) on counting a predetermined number of transitions of the reference signal providing a second count complete signal, and a logic circuit (20) for generating a signal (LOCK) indicating lock has been achieved in response to the receipt of either the first or second count complete signal. Preferably, the lock detection circuit further includes a pulse width detection circuit (30) for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first and second counter.
Inventors
- 👤 Nathan Baron
- 👤 Judah Adelman
- 👤 Yehuda Volpert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:08
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03L7/089; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
190 words
A lock detection circuit for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal, the lock detection circuit comprising: means for generating first and second pulses, the first and second pulses respectively representing positive and negative differences between a parameter of the PLL signal and a parameter of the reference signal; first counting means for counting sets of the first and second pulses, each set comprising a first pulse followed by a second pulse, the first counting means on counting a predetermined number of sets of pulses providing a first count complete signal, the lock detection circuit being characterised by: second counting means for counting transitions of the reference signal, and being coupled to the means for generating whereby the second counting means is reset by the first or second pulses, the second counting means on counting a predetermined number of transitions of the reference signal providing a second count complete signal; and logic means for generating a signal indicating lock has been achieved in response to the receipt of either the first or second count complete signal.
Claim 2
Dependent Claim
190 words
A lock detection circuit for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal, the lock detection circuit comprising: means for generating first and second pulses, the first and second pulses respectively representing positive and negative differences between a parameter of the PLL signal and a parameter of the reference signal; first counting means for counting sets of the first and second pulses, each set comprising a first pulse followed by a second pulse, the first counting means on counting a predetermined number of sets of pulses providing a first count complete signal, the lock detection circuit being characterised by: second counting means for counting transitions of the reference signal, and being coupled to the means for generating whereby the second counting means is reset by the first or second pulses, the second counting means on counting a predetermined number of transitions of the reference signal providing a second count complete signal; and logic means for generating a signal indicating lock has been achieved in response to the receipt of either the first or second count complete signal.
Claim 3
Dependent Claim
21 words
The lock detection circuit according to claim 1 wherein the second counting means counts the failing transitions of the reference signal.
Claim 4
Dependent Claim
117 words
The lock detection circuit according to claim 1 wherein the second counter is a m-bit counter comprising m toggle flip-flops coupled in series, a clock input of the first toggle flip-flop being coupled to receive the reference signal, the reset inputs of each of the m toggle flip-flops being coupled to receive the first and second pulses, the output of the first toggle flip-flop and each following flip-flop being coupled to a clock input of the following toggle flip-flip and to a respective input of a NAND logic gate whereby on counting 2 m -1 transitions of the reference signal the output of the NAND logic gate switches states and thereby provides the second count complete signal.
Claim 5
Dependent Claim
59 words
The lock detection circuit according to claim 1 further comprising a pulse width detection circuit for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first and second counting means.
Claim 6
Dependent Claim
134 words
The lock detection circuit according to claim 4 wherein the pulse width detection circuit comprises: a first RC circuit coupled to the means for generating whereby the first RC circuit is charged to a first voltage level by the first pulse, the first voltage level being dependent on the width of the first pulse; a second RC circuit coupled to the means for generating whereby the second RC circuit is charged to a second voltage level by the second pulse, the second voltage level being dependent on the width of the second pulse; and comparing means for comparing the first voltage level and the second voltage level with a reference voltage and for providing the reset signal if either the first voltage level or the second voltage level is greater than the reference voltage.
Claim 7
Dependent Claim
142 words
The lock detection circuit according to claim 5 wherein the comparing means comprises: a first comparator for comparing the first voltage level with the reference voltage and for providing a first output signal having a first or second state, the first output signal having the first state if the first voltage level is greater than the reference voltage; a second comparator for comparing the second voltage level with the reference voltage and for providing a second output signal having the first or second state, the second output signal having the first state if the second voltage level is greater than the reference voltage level; and an OR logic gate coupled to receive the first and second output signals at first and second inputs thereof for providing the reset signal in response to the first or second output signal having the first state.
Claim 8
Dependent Claim
24 words
The lock detection circuit according to claim 5 wherein the pulse width detection circuit further comprises a voltage divider for providing the reference voltage.
Claim 9
Dependent Claim
239 words
A lock detection circuit for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal, the lock detection circuit comprising: means for generating first and second pulses, the first and second pulses respectively representing positive and negative differences between a parameter of the PLL signal and a parameter of the reference signal; first counting means for counting sets of the first and second pulses, each set comprising a first pulse followed by a second pulse, the first counting means on counting a predetermined number of sets of pulses providing a first count complete signal, the lock detection circuit being characterised by: second counting means for counting transitions of the reference signal, and being coupled to the means for generating whereby the second counting means is reset by the first or second pulses, the second counting means on counting a predetermined number of transitions of the reference signal providing a second count complete signal; logic means for generating a signal indicating lock has been achieved in response to the receipt of either the first or second count complete signal; and a pulse width detection circuit for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first and second counting means.
Claim 10
Dependent Claim
239 words
A lock detection circuit for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal, the lock detection circuit comprising: means for generating first and second pulses, the first and second pulses respectively representing positive and negative differences between a parameter of the PLL signal and a parameter of the reference signal; first counting means for counting sets of the first and second pulses, each set comprising a first pulse followed by a second pulse, the first counting means on counting a predetermined number of sets of pulses providing a first count complete signal, the lock detection circuit being characterised by: second counting means for counting transitions of the reference signal, and being coupled to the means for generating whereby the second counting means is reset by the first or second pulses, the second counting means on counting a predetermined number of transitions of the reference signal providing a second count complete signal; logic means for generating a signal indicating lock has been achieved in response to the receipt of either the first or second count complete signal; and a pulse width detection circuit for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first and second counting means.
Claim 11
Dependent Claim
134 words
The lock detection circuit according to claim 8 wherein the pulse width detection circuit comprises: a first RC circuit coupled to the means for generating whereby the first RC circuit is charged to a first voltage level by the first pulse, the first voltage level being dependent on the width of the first pulse; a second RC circuit coupled to the means for generating whereby the second RC circuit is charged to a second voltage level by the second pulse, the second voltage level being dependent on the width of the second pulse; and comparing means for comparing the first voltage level and the second voltage level with a reference voltage and for providing the reset signal if either the first voltage level or the second voltage level is greater than the reference voltage.
Claim 12
Dependent Claim
142 words
The lock detection circuit according to claim 9 wherein the comparing means comprises: a first comparator for comparing the first voltage level with the reference voltage and for providing a first output signal having a first or second state, the first output signal having the first state if the first voltage level is greater than the reference voltage; a second comparator for comparing the second voltage level with the reference voltage and for providing a second output signal having the first or second state, the second output signal having the first state if the second voltage level is greater than the reference voltage level; and an OR logic gate coupled to receive the first and second output signals at first and second inputs thereof for providing the reset signal in response to the first or second output signal having the first state.
Claim 13
Dependent Claim
146 words
A lock detection circuit for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal, the lock detection circuit comprising: means for generating first and second pulses, the first and second pulses respectively representing positive and negative differences between a parameter of the PLL signal and a parameter of the reference signal; first counting means for counting the first and second pulses, the first counting means on counting a predetermined number of pulses providing a signal indicating lock has been achieved, the lock detection circuit being characterised by: a pulse width detection circuit for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first counting means.
Claim 14
Dependent Claim
146 words
A lock detection circuit for a phase lock loop (PLL) for detecting when a signal generated by the PLL is substantially locked to a reference signal, the lock detection circuit comprising: means for generating first and second pulses, the first and second pulses respectively representing positive and negative differences between a parameter of the PLL signal and a parameter of the reference signal; first counting means for counting the first and second pulses, the first counting means on counting a predetermined number of pulses providing a signal indicating lock has been achieved, the lock detection circuit being characterised by: a pulse width detection circuit for detecting the widths of the first and second pulses and in response to detecting the width of either of the first or second pulse is greater than a predetermined value for providing a reset signal which resets the first counting means.
Claim 15
Dependent Claim
53 words
The lock detection circuit according to claim 11 wherein the first counting means counts sets of the first a second pulses, each set comprising a first pulse followed by a second pulse, the first counting means providing the first count complete signal in response to counting a predetermined number of sets of pulses.
Claim 16
Dependent Claim
134 words
The lock detection circuit according to claim 11 wherein the pulse width detection circuit comprises: a first RC circuit coupled to the means for generating whereby the first RC circuit is charged to a first voltage level by the first pulse, the first voltage level being dependent on the width of the first pulse; a second RC circuit coupled to the means for generating whereby the second RC circuit is charged to a second voltage level by the second pulse, the second voltage level being dependent on the width of the second pulse; and comparing means for comparing the first voltage level and the second voltage level with a reference voltage and for providing the reset signal if either the first voltage level or the second voltage level is greater than the reference voltage.
Claim 17
Dependent Claim
142 words
The lock detection circuit according to claim 13 wherein the comparing means comprises: a first comparator for comparing the first voltage level with the reference voltage and for providing a first output signal having a first or second state, the first output signal having the first state if the first voltage level is greater than the reference voltage; a second comparator for comparing the second voltage level with the reference voltage and for providing a second output signal having the first or second state, the second output signal having the first state if the second voltage level is greater than the reference voltage level; and an OR logic gate coupled to receive the first and second output signals at first and second inputs thereof for providing the reset signal in response to the first or second output signal having the first state.
Claim 18
Dependent Claim
13 words
A phase lock loop comprising a lock detection circuit according to claim 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |