Semiconductor static RAM having thin film transistor gate connection

Claim 2

A semiconductor memory device comprising: a semiconductor substrate; a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, each of said first and second transfer transistors, said first and second driver transistors and said first and second thin film transistor loads having a source, a drain and a gate electrode; a connection region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are electrically connected; the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load being made of conductor layers which are stacked in succession on said semiconductor substrate, a respective insulator layer being interposed between each two successively stacked conductor layers and thereby defining a bottom conductor layer and successive, intermediate and top conductor layers with respective insulation layers interposed therebetween; and a surface portion of the bottom conductor layer being exposed in the connecting region and at least transverse wall surfaces of each intermediate conductor layer being exposed within the connecting region and the top conductor layer being connected electrically within, and by, the connecting region with the exposed top surface portion of the bottom stacked conductor layer and primarily with the respective transverse wall surfaces of the intermediate, stacked conductor layers.

Claim 3

The semiconductor memory device as claimed in claim 1, wherein the top conductor layer forms the drain of the second thin film transistor load, the bottom conductor layer forms the gate electrode of the first driver transistor, and an intermediate conductor layer, between the top and bottom conductor layers, forms the gate electrode of the first thin film transistor load.

Claim 4

The semiconductor memory device as claimed in claim 2, wherein at least the intermediate conductor layers are made of polysilicon, and the insulator layers are made of SiO 2 .

Claim 5

The semiconductor memory device as claimed in claim 3, wherein the bottom conductor layer comprises a first layer formed on said semiconductor substrate and a second layer formed on the first layer, said second layer being made of a material selected from the group consisting of refractory metals and refractory metal silicides.

Claim 6

The semiconductor memory device as claimed in claim 2, wherein the drain of the second driver transistor is further connected to the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load by said connecting region.

Claim 7

The semiconductor memory device as claimed in claim 1, wherein the first thin film transistor load has a channel region, and the gate electrode of the first thin film transistor load is made up of a lower gate electrode, which is formed under the channel region and separated therefrom by a respective, said interposed insulator layer, and an upper gate electrode, which is formed above the channel region and separated therefrom by a respective, said interposed insulator layer.

Claim 8

The semiconductor memory device as claimed in claim 6, wherein the top conductor layer forms the upper gate electrode of the first thin film transistor load, the bottom conductor layer forms the gate electrode of the first driver transistor, and the conductor layers provided between the top and bottom conductor layers respectively form the drain of the second thin film transistor load and the lower gate electrode of the first thin film transistor load.

Claim 9

The semiconductor memory device as claimed in claim 7, wherein at least each intermediate conductor layer is made of polysilicon and the insulator layers are made of SiO 2 .

Claim 10

The semiconductor memory device as claimed in claim 8, wherein the bottom conductor layer comprises a first layer formed on said semiconductor substrate and a second layer formed on the first layer, said second layer being made of a material selected from the group consisting of refractory metals and refractory metal silicides.

Claim 11

The semiconductor memory device as claimed in claim 7, wherein the drain of the second driver transistor is further connected to the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load by said connecting region.

Claim 12

A semiconductor memory device comprising: a semiconductor substrate; a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, each of said first and second transfer transistors, said first and second driver transistors and said first and second thin film transistor loads having a source, a drain and a gate electrode; a connection region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are electrically connected; the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load being made of conductor layers which are stacked in succession on said semiconductor substrate and a respective insulator layer is interposed between each two successive stacked conductor layers and thereby defining a bottom conductor layer and successive, intermediate and top conductor layers with respective insulation layers interposed therebetween; and the connecting region further comprising: a contact window extending through the successively stacked top and intermediate conductor layers and each interposed insulator layer and exposing a surface portion of the bottom conductor layer, respective transverse wall surfaces of the stacked conductor layers and interposed insulator layers being exposed at and defining corresponding sidewalls of the contact hole, the respective transverse wall surfaces of the stacked conductor layers and the interposed insulator layers, corresponding to each sidewall of the contact hole, being substantially aligned, and a conductor material formed within and covering at least the sidewalls of the contact window and the exposed top surface portion of the bottom conductor layer, the conductor material being formed on at least the exposed transverse wall surfaces of the respective conductor layers and electrically connecting the top conductor layer with the intermediate conductor layers and the bottom layer.

Claim 13

A semiconductor memory device comprising: a semiconductor substrate; a memory cell provided on the semiconductor substrate and including first and second transfer transistors, first and second driver transistors and first and second thin film transistor loads, each of said first and second transfer transistors, said first and second driver transistors and said first and second thin film transistor loads having a source, a drain and a gate electrode; a connection region in which the drain of the second thin film transistor load, the gate electrode of the first thin film transistor load and the gate electrode of the first driver transistor are electrically connected; the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load being made of conductor layers which are stacked in succession on said semiconductor substrate and a respective insulator layer is interposed between each two successive stacked conductor layers and thereby defining a bottom conductor layer and successive, intermediate and top conductor layers with respective insulation layers interposed therebetween; and the connecting region further comprising: a contact window extending through the successively stacked top and intermediate conductor layers and each interposed insulator layer and exposing a surface portion of the bottom conductor layer, respective transverse wall surfaces of the stacked conductor layers and interposed insulator layers being exposed at and defining corresponding sidewalls of the contact hole, the respective transverse wall surfaces of the stacked conductor layers and the interposed insulator layers, corresponding to each sidewall of the contact hole, being substantially aligned, and a conductor material formed within and covering at least the sidewalls of the contact window and the exposed top surface portion of the bottom conductor layer, the conductor material being formed on at least the exposed transverse wall surfaces of the respective conductor layers and electrically connecting the top conductor layer with the intermediate conductor layers and the bottom layer.

Claim 14

The semiconductor memory device as claimed in claim 11, wherein the top conductor layer forms the drain of the second thin film transistor load, the bottom conductor layer forms the gate electrode of the first driver transistor, and an intermediate conductor layer, between the top and bottom conductor layers, forms the gate electrode of the first thin film transistor load.

Claim 15

The semiconductor memory device as claimed in claim 12, wherein at least the intermediate conductor layers are made of polysilicon and the insulator layers are made of SiO 2 .

Claim 16

The semiconductor memory device as claimed in claim 13, wherein the bottom conductor layer comprises a first layer formed on said semiconductor substrate and a second layer formed on the first layer, said second layer being made of a material selected from the group consisting of refractory metals and refractory metal silicides.

Claim 17

The semiconductor memory device as claimed in claim 12, wherein the drain of the second driver transistor is further connected to the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load by said connecting region.

Claim 18

The semiconductor memory device as claimed in claim 11, wherein the first thin film transistor load has a channel region, and the gate electrode of the first thin film transistor load is made up of a lower gate electrode, which is formed under the channel region and separated therefrom by a respective, said interposed insulator layer, and an upper gate electrode, which is formed above the channel region and separated therefrom by a respective, said interposed insulator layer.

Claim 19

The semiconductor memory device as claimed in claim 16, wherein the top conductor layer forms the upper gate electrode of the first thin film transistor load, the bottom conductor layer forms the gate electrode of the first driver transistor, and the conductor layers provided between the top and bottom conductor layers respectively form the drain of the second thin film transistor load and the lower gate electrode of the first thin film transistor load.

Claim 20

The semiconductor memory device as claimed in claim 7, wherein at least each intermediate conductor layer is made of polysilicon and the insulator layers are made of SiO 2 .

Claim 21

The semiconductor memory device as claimed in claim 8, wherein the bottom conductor layer comprises a first layer formed on said semiconductor substrate and a second layer formed on the first layer, said second layer being made of a material selected from the group consisting of refractory metals and refractory metal silicides.

Claim 22

The semiconductor memory device as claimed in claim 7, wherein the drain of the second driver transistor is further connected to the gate electrode of the first driver transistor, the gate electrode of the first thin film transistor load and the drain of the second thin film transistor load by said connecting region.

Claim 23

The semiconductor memory device as recited in claim 18, wherein the transverse wall surfaces of the conductor layers protrude inwardly of the transverse wall surfaces of the corresponding insulator layers at each sidewall of the contact hole, the conductor material, further, being formed on and connected to the protruding surfaces of the intermediate conductor layers.