Patent US5326711A successfully refreshed from Google Patents.
US5326711A
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High performance high voltage vertical transistor and method of fabrication
Assignee: Texas Instruments Inc
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Filing: 1993-01-04
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Granted: 1994-07-05
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Expires: 2013-01-04
Abstract
Abstract A transistor device (10) includes an epitaxial layer (14) formed on a semiconductor substrate layer (12). A base layer (16) is formed on the epitaxial layer (14) and a source layer (18) is formed on the base layer (16). A trench region (22) is formed extending through the source layer (18), the base layer (16), and the epitaxial layer (14) and into the semiconductor substrate layer (12). An oxide layer (24) is formed on the source layer (18) and on the internal walls of the trench region (22) such that the oxide layer (24) is wider at the bottom of the trench region (22) than at the top in order to handle high voltage applications. A gate layer (26) is formed within the trench region (22) on the oxide layer (24). The gate layer (26) causes a drift region formed within the epitaxial layer (14) to fully deplete under full rated blocking conditions, decreasing the drift region component of the on-resistance which is the dominant parameter in very high voltage devices.
Inventors
- 👤 Satwinder Malhi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/66; H10D30/668; H10D12/00; H10D12/01; H10D12/031; H10D12/032; H10D12/038; H10D12/411; H10D12/441; H10D12/461; H10D12/481; H10D30/63; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/514; H10D64/516; H10D64/517; H10D64/519
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
254 words
A method of fabricating a high performance high voltage transistor at a face of a semiconductor substrate, comprising the steps of: growing an epitaxial layer of a first conductivity type on the semiconductor substrate such that a drift region forms within said epitaxial layer; diffusing a base layer of a second conductivity type on said epitaxial layer; diffusing a source layer of said first conductivity type on said base layer such that a channel forms within said base layer; forming a trench region through said source layer, said base layer, and said epitaxial layer and into the semiconductor substrate; depositing a thick oxide layer on said source layer and inner walls of said trench region; depositing a thick gate layer of said first conductivity type on said thick oxide layer and within said trench region; removing a portion of said thick gate layer above said source layer; removing a portion of said thick oxide layer such that a remaining thick oxide layer does not extend beyond said epitaxial layer; depositing a thin oxide layer onto said source layer, said thick oxide layer, said thick gate layer, and said inner walls of said trench region; depositing a thin gate layer of said first conductivity type on said thin oxide layer; removing said thin gate layer and said thin oxide layer from a lateral surface of said thick gate layer; and depositing a second thick gate layer of said first conductivity type on said thin gate layer and said lateral surface of said thick gate layer.
Claim 2
Independent Claim
254 words
A method of fabricating a high performance high voltage transistor at a face of a semiconductor substrate, comprising the steps of: growing an epitaxial layer of a first conductivity type on the semiconductor substrate such that a drift region forms within said epitaxial layer; diffusing a base layer of a second conductivity type on said epitaxial layer; diffusing a source layer of said first conductivity type on said base layer such that a channel forms within said base layer; forming a trench region through said source layer, said base layer, and said epitaxial layer and into the semiconductor substrate; depositing a thick oxide layer on said source layer and inner walls of said trench region; depositing a thick gate layer of said first conductivity type on said thick oxide layer and within said trench region; removing a portion of said thick gate layer above said source layer; removing a portion of said thick oxide layer such that a remaining thick oxide layer does not extend beyond said epitaxial layer; depositing a thin oxide layer onto said source layer, said thick oxide layer, said thick gate layer, and said inner walls of said trench region; depositing a thin gate layer of said first conductivity type on said thin oxide layer; removing said thin gate layer and said thin oxide layer from a lateral surface of said thick gate layer; and depositing a second thick gate layer of said first conductivity type on said thin gate layer and said lateral surface of said thick gate layer.
Claim 3
Dependent Claim
57 words
The method of claim 1, further comprising the step of: forming a vertical region of said first conductivity type extending through said base layer to said epitaxial layer, said base layer separates said vertical region from said source layer such that said channel forms laterally within said base layer between said source layer and said vertical region.
Claim 4
Dependent Claim
22 words
The method of claim 1, wherein the semiconductor substrate has said first conductivity type to form a double-diffused metal oxide semiconductor transistor.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein the semiconductor substrate has said second conductivity type to form an insulated gate bipolar transistor.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
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