Digital sigma-delta modulator and arithmetic overflow protected adder

Claim 2

In a digital sigma-delta modulator with multi-phase operations by time-shared means including an adder to produce multiple integration, an arrangement comprising: switching means for alternately establishing one of: a connection between a first input of the adder and an input of the modulator; and connections between the adder output and the first input of the adder by way of a first integration delay circuit, and the adder output and a second input of the adder by way of a second delay circuit.

Claim 3

The digital sigma-delta modulator arrangement as in claim 1, wherein the switching means is coupled to the input of the modulator during a first integration and to both the first and second delay circuits during subsequent integrations.

Claim 4

The digital sigma-delta modulator arrangement as in claim 1, wherein at least one of the adder inputs is fed through at least two delay circuits in cascade.

Claim 5

The digital sigma-delta modulator arrangement as in claim 3, wherein the first delay circuit is disposed nearest the adder output and feeds the adder input not fed through the at least two delay circuits in cascade.

Claim 6

The digital sigma-delta modulator arrangement as in claim 4, wherein the first delay circuit disposed nearest the adder output feeds the other adder input through the switching means.

Claim 7

The digital sigma-delta modulator arrangement as in claim 4, wherein the first delay circuit disposed nearest the adder output feeds a modulator quantizer.

Claim 8

The digital sigma-delta modulator arrangement as in claim 6, wherein the modulator quantizer is coupled to an output of the modulator through output switching means.

Claim 9

The digital sigma-delta modulator arrangement as in claim 7, wherein the modulator quantizer provides a one bit output signal.

Claim 10

The digital sigma-delta modulator arrangement as in claim 6, wherein a third delay circuit couples an output of the modulator quantizer to the first adder input through the switching means during the first integration.

Claim 11

The digital sigma-delta modulator arrangement as in claim 9, wherein the third delay circuit produces a delay corresponding to a clock period of the modulator.

Claim 12

The digital sigma-delta modulator arrangement as in claim 6, wherein the modulator quantizer produces a delay corresponding to a clock period of the modulator.

Claim 13

The digital sigma-delta modulator arrangement as in claim 3, wherein the number of cascaded delay circuits is equal to mn where m is a positive integer representing the number of independent input/output pairs sharing the modulator in time division multiplex fashion and n is a positive integer larger than unity representing the number of integrations.

Claim 14

The digital sigma-delta modulator arrangement as in claim 12, wherein each of the cascaded delay circuits provides a delay which corresponds to a clock period of the modulator and that a modulator sampling period is equal to mn clock periods.

Claim 15

The digital sigma-delta modulator arrangement as in claim 1, wherein said adder is a multibit parallel adder for adding signals.

Claim 16

The digital sigma-delta modulator arrangement as in claim 14, wherein all multibit adder signals are in two's complement form.

Claim 17

The digital sigma-delta modulator arrangement as in claim 1, wherein the switching means is coupled to the input of the modulator during a first integration and to both delay circuits during subsequent integrations, wherein one of the adder inputs is fed through at least two delay circuits in cascade, and wherein during the last of said subsequent integrations, switching means feed the inverse of the second most significant bit of a signal at the output of the delay circuit nearest the adder output, to the delay circuit feeding the other input of the adder, to act as the most significant bits of the signal.

Claim 18

The digital sigma-delta modulator arrangement as in claim 16, wherein during the first integration, the inverse of the quantizer bit replaces at least the most significant bit of the adder input prior to actually feeding the switching means.

Claim 19

The digital sigma-delta modulator arrangement as in claim 1, wherein the second delay circuit is coupled indirectly to the second adder input during the first integration via said switching means and a leakage logic circuit in a first condition and directly to the adder through said switching means in a second condition.

Claim 20

The digital sigma-delta modulator arrangement as in claim 1, wherein said adder comprises: a multibit adder for binary values in two's complement form having an arithmetic overflow detector controlling an adder output logic circuit to produce a maximum range output signal when the sum would otherwise be out of range, wherein the detector feeds a positive or a negative overflow signal to the logic circuit when the most significant bit of the adder output signal differs from both the most significant bits of the two adder input signals also fed to the detector, whereby for such overflow conditions the logic circuit modifies the adder output signal to produce a logic circuit output signal with a most significant bit differing from all other bits.

Claim 21

A digital sigma-delta modulator comprising: adder means having at least first and second inputs and an output; integration delay means, operatively coupled with the adder means, for delaying the output of the adder; second delay means, operatively coupled with the integration delay means, for providing a second delayed output; first switching means, operatively coupled with the second delay means, for selectively providing the output from the second delay means one of directly and through a leakage logic circuit, to the second input of the adder means; modulator quantizer means, operatively coupled with the integration delay means, for receiving an output from the integration delay means and providing the modulator output through an output buffer switch; first inverter means, operatively coupled with the modulator quantizer means, for receiving an output from the modulator quantizer means and providing a first inverted output; third delay means, operatively coupled with the first inverter means, for providing a third delayed output; input switching means, operatively coupled with the first input of the adder means, the integration delay means, the third delay means, and the input of the modulator, for selectively providing input to the first input of the adder, the input of the modulator being provided by input lines including second inverting means, for inverting at least a most significant bit of the modulator input and providing the inverted bit to the input switching means; and third inverting means, operatively coupled with the integration delay means and the second delay means, for selectively providing an inverted output to the second delay means of an output from the integration delay means.

Claim 22

A digital sigma-delta modulator comprising: adder means having at least first and second inputs and an output; integration delay means, operatively coupled with the adder means, for delaying the output of the adder; second delay means, operatively coupled with the integration delay means, for providing a second delayed output; first switching means, operatively coupled with the second delay means, for selectively providing the output from the second delay means one of directly and through a leakage logic circuit, to the second input of the adder means; modulator quantizer means, operatively coupled with the integration delay means, for receiving an output from the integration delay means and providing the modulator output through an output buffer switch; first inverter means, operatively coupled with the modulator quantizer means, for receiving an output from the modulator quantizer means and providing a first inverted output; third delay means, operatively coupled with the first inverter means, for providing a third delayed output; input switching means, operatively coupled with the first input of the adder means, the integration delay means, the third delay means, and the input of the modulator, for selectively providing input to the first input of the adder, the input of the modulator being provided by input lines including second inverting means, for inverting at least a most significant bit of the modulator input and providing the inverted bit to the input switching means; and third inverting means, operatively coupled with the integration delay means and the second delay means, for selectively providing an inverted output to the second delay means of an output from the integration delay means.