Patent US5325368A successfully refreshed from Google Patents.
US5325368A
Expired / Lapsed
US
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JTAG component description via nonvolatile memory
Assignee: NCR Voyix Corp
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Filing: 1991-11-27
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Granted: 1994-06-28
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Expires: 2011-11-27
Abstract
Abstract Nonvolatile memory is provided on each module of a computer system including one or more modules with each module including a plurality of components including JTAG technology. A test bus operable in accordance with the 1149.1 standard is included in the computer system and is arranged to access the nonvolatile memory. Boundary scan information for the components on a module and also additional information, preferably fully describing all JTAG related characteristics and operations, is stored in the nonvolatile memory. A JTAG bus system is then able to access the module memory and obtain all information required to fully implement JTAG operations for the module.
Inventors
- 👤 Larry C. James
- 👤 Mark A. Taylor
- 👤 Chris A. Harrison
- 👤 David L. Simpson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G01R31/318561; G01R31/31702
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A method of operating a test bus incorporated into a computer system including one or more modules each of which includes a plurality of components each in turn including boundary scan architecture for testing said components via said test bus, said method comprising the steps of: providing nonvolatile memory on each of said one or more modules, said nonvolatile memory being accessible by said test bus; storing boundary scan information for each of said plurality of components in said nonvolatile memory; and accessing said nonvolatile memory to retrieve boundary scan information required by said test bus for testing said plurality of components.
Claim 2
Independent Claim
102 words
A method of operating a test bus incorporated into a computer system including one or more modules each of which includes a plurality of components each in turn including boundary scan architecture for testing said components via said test bus, said method comprising the steps of: providing nonvolatile memory on each of said one or more modules, said nonvolatile memory being accessible by said test bus; storing boundary scan information for each of said plurality of components in said nonvolatile memory; and accessing said nonvolatile memory to retrieve boundary scan information required by said test bus for testing said plurality of components.
Claim 3
Dependent Claim
66 words
A method of operating a test bus incorporated into a computer system as claimed in claim 1 wherein the step of storing boundary scan information for each of said plurality of components in said nonvolatile memory comprises the step of entering each component into a scan path table which identifies each component to said test bus and directs said test bus to additional component information tables.
Claim 4
Dependent Claim
54 words
A method of operating a test bus incorporated into a computer system as claimed in claim 2 wherein the step of storing boundary scan information for each of said plurality of components in said nonvolatile memory further comprises the step of entering component specific information for each different one of said plurality of components.
Claim 5
Dependent Claim
59 words
A method of operating a test bus incorporated into a computer system as claimed in claim 3 wherein the step of storing boundary scan information for each of said plurality of components in said nonvolatile memory further comprises the step of entering instruction decoding information for instructions to be performed by the test bus on said plurality of components.
Claim 6
Dependent Claim
88 words
A module for use in a computer system including one or more of said modules and a serial test bus, said module comprising: module test means for interfacing said module with said serial test bus; a plurality of components mounted on said module, said plurality of components being connected to said test bus through said module test means for testing said components; and nonvolatile memory means accessible by said test bus through said module test means for storing boundary scan information for each of said plurality of components.
Claim 7
Dependent Claim
88 words
A module for use in a computer system including one or more of said modules and a serial test bus, said module comprising: module test means for interfacing said module with said serial test bus; a plurality of components mounted on said module, said plurality of components being connected to said test bus through said module test means for testing said components; and nonvolatile memory means accessible by said test bus through said module test means for storing boundary scan information for each of said plurality of components.
Claim 8
Dependent Claim
41 words
A module for use in a computer system including one or more of said modules and a serial test bus as claimed in claim 5 wherein said nonvolatile memory means comprises scan path storage means for identifying each of said components.
Claim 9
Dependent Claim
72 words
A module for use in a computer system including one or more of said modules and a serial test bus as claimed in claim 6 wherein said nonvolatile memory means further comprises component specific storage means for storing information for each different one of said plurality of components on said module, said scan path storage means further identifying memory locations within said component specific storage means corresponding to each of said components.
Claim 10
Dependent Claim
61 words
A module for use in a computer system including one or more of said modules and a serial test bus as claimed in claim 7 wherein said nonvolatile memory means further comprises instruction decoding storage means for storing instruction decoding information used by said test bus to decode instructions to be performed by the test bus on said plurality of components.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |