Patent US6513046B1 successfully refreshed from Google Patents.
Patent US5325320A successfully refreshed from Google Patents.
US5325320A
Expired / Lapsed
US
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Area efficient multiplier for use in an integrated circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-05-01
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Granted: 1994-06-28
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Expires: 2012-05-01
Abstract
Abstract A high-speed multiplier utilizing a layout architecture requiring very little area on a chip. The present invention employs a floor plan which exemplifies regularity and is approximately 33.3% more compact than conventional Wallace Trees. During a first phase of a first clock cycle, Booth coding takes place resulting in a first group of partial products. In a second phase of the first clock cycle, the first group of partial products are input into a first and a second carry-save adder. Results from the second carry-save adder are latched in a first and second register. Also during the second phase of the first clock cycle, a second group of partial products are Booth coded. In a first phase of a cycle 2, the second group of partial products are input into the first and second carry-save adders. Results from the second carry-save adder are latched into a third and fourth register. In a second phase of cycle 2, results from the first, second, third and fourth registers are input into a third and fourth carry-save adder. The outputs from the fourth carry-save adder are latched into a fifth and a sixth register. In a first phase of a cycle 3, results latched in the fifth and sixth registers are input into a CPA. The CPA then generates a final output for the multiplier.
Inventors
- 👤 Chiao-Er A. Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:30
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5324; A; A61; A61M; A61M2210/00; A61M2210/10; A61M2210/1042; A61M2210/1075; G06F7/533; G06F7/5334; G06F7/5336; G06F7/5338
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
73 words
A high-speed multiplier, comprising: a first carry-save adder (CSA); a second CSA coupled to said first CSA; first, second, third, and fourth registers coupled to said second CSA; a third CSA coupled to said first, said second and said third registers; a fourth CSA coupled to said fourth register and said third CSA; fifth and sixth registers coupled to said fourth CSA; and a carry-propagate adder coupled to said fifth and sixth registers.
Claim 2
Dependent Claim
73 words
A high-speed multiplier, comprising: a first carry-save adder (CSA); a second CSA coupled to said first CSA; first, second, third, and fourth registers coupled to said second CSA; a third CSA coupled to said first, said second and said third registers; a fourth CSA coupled to said fourth register and said third CSA; fifth and sixth registers coupled to said fourth CSA; and a carry-propagate adder coupled to said fifth and sixth registers.
Claim 3
Dependent Claim
204 words
A compact integrated circuit multiplier having Booth coded partial products as inputs, comprising: a first carry-save adder for receiving a plurality of partial product inputs and for generating a first sum and a first carry; a second carry-save adder, coupled to said first carry-save adder for receiving a further partial product input and said first sum and said first carry as inputs, and for generating a second sum and a second carry; registers means coupled to said second carry-save adder, for storing said second sum and said second carry; a third carry-save adder, coupled to said register means, for receiving said second sum and said second carry from said register means and for generating a third carry and a third sum; a fourth carry-save adder, coupled to said register means and said third carry-save adder, for receiving said second carry from said register means and for receiving said third carry and said third sum from said third carry-save adder, and for generating a fourth carry and a fourth sum; and a carry propagate adder, coupled to said fourth carry-save adder, for receiving said fourth carry and said fourth sum, and for adding said fourth carry with said fourth sum to obtain a final product.
Claim 4
Dependent Claim
204 words
A compact integrated circuit multiplier having Booth coded partial products as inputs, comprising: a first carry-save adder for receiving a plurality of partial product inputs and for generating a first sum and a first carry; a second carry-save adder, coupled to said first carry-save adder for receiving a further partial product input and said first sum and said first carry as inputs, and for generating a second sum and a second carry; registers means coupled to said second carry-save adder, for storing said second sum and said second carry; a third carry-save adder, coupled to said register means, for receiving said second sum and said second carry from said register means and for generating a third carry and a third sum; a fourth carry-save adder, coupled to said register means and said third carry-save adder, for receiving said second carry from said register means and for receiving said third carry and said third sum from said third carry-save adder, and for generating a fourth carry and a fourth sum; and a carry propagate adder, coupled to said fourth carry-save adder, for receiving said fourth carry and said fourth sum, and for adding said fourth carry with said fourth sum to obtain a final product.
Claim 5
Dependent Claim
34 words
The multiplier of claim 2, wherein said register means comprises a first register and a second register, said first register for storing said second sum, and said second register for storing said second carry.
Claim 6
Dependent Claim
34 words
The multiplier of claim 2, wherein said register means comprises a third register and a fourth register, said third register for storing said second sum and said fourth register for storing said second carry.
Claim 7
Dependent Claim
70 words
The multiplier of claim 2, further comprising a fifth register and a sixth register coupled between said fourth carry-save adder and said carry-propagate adder, said fifth register for storing said fourth sum from said fourth carry-save adder before passing said fourth sum to said carry-propagate adder, and said sixth register for storing said fourth carry from said fourth carry-save adder before passing said fourth carry to said carry propagate adder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |