US5325241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Write precompensation with frequency synthesizer
Assignee: Fujitsu Ltd
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Filing: 1991-06-14
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Granted: 1994-06-28
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Expires: 2011-06-14
Abstract
Abstract A write precompensation circuit employs a frequency synthesizer for providing a variable timing signal linked to variable transfer rate in a track zone recording system of a disk drive. The synthesizer also provides an operating frequency current sense signal that is used to generate bit shift of data bits being recorded. A ramp voltage on a ramp capacitor and a logic signal from a bit shift decision circuit are determinative of the magnitude and direction of bit shift, early or late. The VCO and its capacitor are formed on the same IC chip as the ramp capacitor thereby minimizing mismatch due to tolerances inherent in production and operation of electrical components.
Inventors
- 👤 Rodney A. L. Mattison
- 👤 David E. Norton, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:56
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/10009; G11B20/10046; G11B20/10194; G11B20/14; G11B20/1403; G11B20/12; G11B20/1217; G11B20/1258
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
87 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a controllable precomposition signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; and a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal.
Claim 2
Independent Claim
87 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a controllable precomposition signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; and a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal.
Claim 3
Dependent Claim
62 words
A system as in claim 1, wherein said precompensation circuit includes a bit shift decision circuit for shifting the write pulses to be recorded, said decision circuit including combinatorial logic and a shift register for storing defined groups of data bits, and means for providing coded data bits to said decision circuit for shifting said pulses to be recorded early or late.
Claim 4
Dependent Claim
21 words
A system as in claim 1, including a voltage controlled oscillator connected to said pulse locked loop and said control loop.
Claim 5
Dependent Claim
62 words
A system as in claim 3, wherein the phase locked loop of said frequency synthesizer comprises a phase detector, means for providing a timing signal of fixed frequency, a first divider coupled between said phase detector and said timing signal providing means, and a second divider coupled between the output of said voltage controlled oscillator and the input to said phase detector.
Claim 6
Dependent Claim
20 words
A system as in claim 2, wherein said oscillator includes a capacitor and said precompensation circuit includes a ramp capacitor.
Claim 7
Dependent Claim
26 words
A system as in claim 5, wherein said capacitors are formed on an integral semiconductor chip so that a constant matched ratio is maintained during recording.
Claim 8
Dependent Claim
30 words
A system as in claim 5, including a squelch circuit coupled to said ramp capacitor for switching the ramp capacitor to conduct when a data bit to be recorded occurs.
Claim 9
Independent Claim
168 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a precompensation signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal; a voltage controlled oscillator connected to said phase locked loop and said control loop, said voltage controlled oscillator including a capacitor and said precompensation circuit including a ramp circuit; and a plurality of comparators connected to said ramp capacitor, means for applying a reference voltage to said comparators, a multiplexer coupled to receive the output signal from said comparators, and a bit decision circuit coupled to the input of said multiplexer for providing a logic signal to shift the data bit being recorded.
Claim 10
Independent Claim
168 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a precompensation signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal; a voltage controlled oscillator connected to said phase locked loop and said control loop, said voltage controlled oscillator including a capacitor and said precompensation circuit including a ramp circuit; and a plurality of comparators connected to said ramp capacitor, means for applying a reference voltage to said comparators, a multiplexer coupled to receive the output signal from said comparators, and a bit decision circuit coupled to the input of said multiplexer for providing a logic signal to shift the data bit being recorded.
Claim 11
Independent Claim
134 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a precompensation signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; and a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal; and a voltage controlled oscillator connected to said phase locked loop and said control loop; said phase locked loop including a filter coupled to the input of said voltage controlled oscillator, and said control loop including a window comparator coupled to a junction between said filter and oscillator.
Claim 12
Independent Claim
134 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a precompensation signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; and a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal; and a voltage controlled oscillator connected to said phase locked loop and said control loop; said phase locked loop including a filter coupled to the input of said voltage controlled oscillator, and said control loop including a window comparator coupled to a junction between said filter and oscillator.
Claim 13
Dependent Claim
65 words
A system as in claim 9, wherein said control loop includes a microprocessor connected to receive a compare bit signal from said window comparator, a digital-to-analog converter connected to said microprocessor for providing a current signal in response to said compare bit signal, and a source of current reference coupled between said converter and said oscillator for varying the nominal operating frequency of said oscillator.
Claim 14
Independent Claim
102 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a precompensation signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal; and a mirroring circuit coupled to said frequency synthesizer for receiving said operating frequency current sense signal.
Claim 15
Independent Claim
102 words
A system for recording binary data on a magnetic disk having a plurality of data tracks divided into track zones comprising: a write precompensation circuit for providing a precompensation signal to data bits being recorded; a frequency synthesizer including a phase locked loop for generating a variable timing signal and supplying the variable timing signal to said write precompensation circuit; a control loop coupled to said phase locked loop for producing an operating frequency current sense signal to control the magnitude of said precompensation signal; and a mirroring circuit coupled to said frequency synthesizer for receiving said operating frequency current sense signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |