US4334250A
Expired / Lapsed
US
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MFM data encoder with write precompensation
Assignee: Tektronix Inc
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Filing: 1979-09-12
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Granted: 1982-06-08
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Expires: 1999-09-12
Abstract
Abstract A circuit is provided for encoding digital data to be recorded on high-density magnetic storage media. The circuit converts serial data to modified phase modulation encoded serial data with time encoding or write precompensation.
Inventors
- 👤 John G. Theus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:33
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10194
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
202 words
An encoding circuit for converting an input stream of serial data bits to an MFM encoded output stream of serial data bits with write precompensation; said encoding circuit comprising: means for converting the input stream of serial data bits to parallel bits; memory means for storing therein addressable 8-bit words from which said encoded output is to be formed, each said 8-bit word representing an input bit in MFM encoding and at least one of said 8-bit words additionally including write precompensation encoding, the input of said memory means being coupled to said converting means whereby said 8-bit words are addressable by said parallel data bits; said memory means being arranged such that for each parallel data bit a said 8-bit word representing it is made available at the output of said memory means, said word being selectable from those which include precompensation encoding when the context of said parallel data bit so required; means coupled to the output of said memory means for converting said addressable 8-bit words from parallel to serial form providing the output stream of serial data bits; and means for controlling the transfer of said addressable 8-bit words from said memory means to said parallel-to-serial converter means.
Claim 2
Dependent Claim
202 words
An encoding circuit for converting an input stream of serial data bits to an MFM encoded output stream of serial data bits with write precompensation; said encoding circuit comprising: means for converting the input stream of serial data bits to parallel bits; memory means for storing therein addressable 8-bit words from which said encoded output is to be formed, each said 8-bit word representing an input bit in MFM encoding and at least one of said 8-bit words additionally including write precompensation encoding, the input of said memory means being coupled to said converting means whereby said 8-bit words are addressable by said parallel data bits; said memory means being arranged such that for each parallel data bit a said 8-bit word representing it is made available at the output of said memory means, said word being selectable from those which include precompensation encoding when the context of said parallel data bit so required; means coupled to the output of said memory means for converting said addressable 8-bit words from parallel to serial form providing the output stream of serial data bits; and means for controlling the transfer of said addressable 8-bit words from said memory means to said parallel-to-serial converter means.
Claim 3
Dependent Claim
19 words
The encoding circuit according to claim 1 wherein said memory means comprises a ROM for storing 32 8-bit words.
Claim 4
Dependent Claim
18 words
The encoding circuit according to claim 1 wherein said serial-to-parallel converting means comprises a serial-input, parallel-output shift register.
Claim 5
Dependent Claim
18 words
The encoding circuit according to claim 1 wherein said parallel-to-serial converting means comprises a parallel-input, serial-output shift register.
Claim 6
Dependent Claim
15 words
The encoding circuit according to claim 1 wherein said transfer control means comprises D-type flip-flops.
Claim 7
Dependent Claim
15 words
The encoding circuit of claim 1 further comprising means for selecting said write precompensation encoding.
Claim 8
Dependent Claim
214 words
An encoding circuit for converting an input stream of serial data bits to an MFM encoded output stream of serial data bits with write precompensation; said encoding circuit comprising: a serial-input, parallel-output shift register for converting the input stream of serial data bits to parallel bits; a read-only memory for storing therein addressable 8-bit words from which said encoded output is to be formed, each said 8-bit word representing an input bit in MFM encoding and at least one of said 8-bit words additionally including write precompensation encoding, the input of said read-only memory being coupled to said serial-input, parallel-output shift register whereby said 8-bit words are addressable by said parallel data bits; said read-only memory being arranged such that for each parallel data bit a said 8-bit word representing it is made available at the output of said read-only memory, said word being selectable from those which include precompensation encoding when the context of said parallel data bit so requires; a parallel-input, serial-output shift register coupled to the output of said read-only memory for converting said addressable 8-bit words from parallel to serial form providing the output stream of serial data bits; and means for controlling the transfer of said addressable 8-bit words from said read-only memory to said parallel-input, serial-output shift register.
Claim 9
Dependent Claim
214 words
An encoding circuit for converting an input stream of serial data bits to an MFM encoded output stream of serial data bits with write precompensation; said encoding circuit comprising: a serial-input, parallel-output shift register for converting the input stream of serial data bits to parallel bits; a read-only memory for storing therein addressable 8-bit words from which said encoded output is to be formed, each said 8-bit word representing an input bit in MFM encoding and at least one of said 8-bit words additionally including write precompensation encoding, the input of said read-only memory being coupled to said serial-input, parallel-output shift register whereby said 8-bit words are addressable by said parallel data bits; said read-only memory being arranged such that for each parallel data bit a said 8-bit word representing it is made available at the output of said read-only memory, said word being selectable from those which include precompensation encoding when the context of said parallel data bit so requires; a parallel-input, serial-output shift register coupled to the output of said read-only memory for converting said addressable 8-bit words from parallel to serial form providing the output stream of serial data bits; and means for controlling the transfer of said addressable 8-bit words from said read-only memory to said parallel-input, serial-output shift register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-06-07 | 1985-12-07 | 1986-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-06-07 | 1989-12-07 | 1990-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-06-07 | 1993-12-07 | 1994-06-08 | $7700.00 | Window Closed / Lapsed |