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US3879342A Expired / Lapsed US ⏱️ 0.0 years remaining

Pre-recorded digital data compensation system

Assignee: Bull HN Information Systems Italia SpA
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Filing: 1973-12-28
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Granted: 1975-04-22
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Expires: 1993-12-28
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Abstract

Abstract A data compensation system as provided within a digital data magnetic recording system. The data compensation system detects and corrects for certain patterns of digitally encoded pulses which would otherwise result in undesirable pulse shifting when these patterns are recorded and subsequently retrieved. In a preferred embodiment, the data compensation detects and compensates for pulse shifting occurring in two specific patterns of encoded pulses. One pattern of encoded pulses requires that a particular pulse within the pattern be advanced whereas the other pattern requires that a particular pulse within the pattern be delayed. The specific patterns of encoded pulses occur in threefrequency encoded data.

Inventors

  • 👤 Ramesh S Patel

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 12:37
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; G11B20/10046; G11B20/10194

Claims Analysis

Total Claims: 20
Claim 1
Independent Claim 212 words
In a digital data recording system wherein digital data is pulse encoded in the three frequency digital code with the leading edge of a pulse occurring in the middle of a binary one bit cell and at the junction between successive binary zero bit cells so that pulses are spaced from each other in multiples of one-half bit cell increments, said pulse encoded data being in a form for subsequent recording on a magnetic medium and wherein certain patterns of encoded pulses produce pulse shifting when subsequently retrieved, a digital data compensation system which compensates for such pulse shifting prior to the recording of these pulses on the magnetic medium said compensation system comprising: means for temporarily storing a sequence of encoded pulses in one-half bit cell increments so as to thereby form at any one time a pattern of stored pulses; means for decoding the pattern of stored pulses so as to detect when either of two particular patterns of stored pulses is present in said temporary storage means; and means, responsive to said decoding means, for shifting a pulse within the particular pattern of stored pulses a defined amount so as to cancel out the pulse shift which would otherwise appear when the particular pattern is recorded and suBsequently retrieved.
Claim 2
Dependent Claim 212 words
In a digital data recording system wherein digital data is pulse encoded in the three frequency digital code with the leading edge of a pulse occurring in the middle of a binary one bit cell and at the junction between successive binary zero bit cells so that pulses are spaced from each other in multiples of one-half bit cell increments, said pulse encoded data being in a form for subsequent recording on a magnetic medium and wherein certain patterns of encoded pulses produce pulse shifting when subsequently retrieved, a digital data compensation system which compensates for such pulse shifting prior to the recording of these pulses on the magnetic medium said compensation system comprising: means for temporarily storing a sequence of encoded pulses in one-half bit cell increments so as to thereby form at any one time a pattern of stored pulses; means for decoding the pattern of stored pulses so as to detect when either of two particular patterns of stored pulses is present in said temporary storage means; and means, responsive to said decoding means, for shifting a pulse within the particular pattern of stored pulses a defined amount so as to cancel out the pulse shift which would otherwise appear when the particular pattern is recorded and suBsequently retrieved.
Claim 3
Dependent Claim 212 words
In a digital data recording system wherein digital data is pulse encoded in the three frequency digital code with the leading edge of a pulse occurring in the middle of a binary one bit cell and at the junction between successive binary zero bit cells so that pulses are spaced from each other in multiples of one-half bit cell increments, said pulse encoded data being in a form for subsequent recording on a magnetic medium and wherein certain patterns of encoded pulses produce pulse shifting when subsequently retrieved, a digital data compensation system which compensates for such pulse shifting prior to the recording of these pulses on the magnetic medium said compensation system comprising: means for temporarily storing a sequence of encoded pulses in one-half bit cell increments so as to thereby form at any one time a pattern of stored pulses; means for decoding the pattern of stored pulses so as to detect when either of two particular patterns of stored pulses is present in said temporary storage means; and means, responsive to said decoding means, for shifting a pulse within the particular pattern of stored pulses a defined amount so as to cancel out the pulse shift which would otherwise appear when the particular pattern is recorded and suBsequently retrieved.
Claim 4
Dependent Claim 212 words
In a digital data recording system wherein digital data is pulse encoded in the three frequency digital code with the leading edge of a pulse occurring in the middle of a binary one bit cell and at the junction between successive binary zero bit cells so that pulses are spaced from each other in multiples of one-half bit cell increments, said pulse encoded data being in a form for subsequent recording on a magnetic medium and wherein certain patterns of encoded pulses produce pulse shifting when subsequently retrieved, a digital data compensation system which compensates for such pulse shifting prior to the recording of these pulses on the magnetic medium said compensation system comprising: means for temporarily storing a sequence of encoded pulses in one-half bit cell increments so as to thereby form at any one time a pattern of stored pulses; means for decoding the pattern of stored pulses so as to detect when either of two particular patterns of stored pulses is present in said temporary storage means; and means, responsive to said decoding means, for shifting a pulse within the particular pattern of stored pulses a defined amount so as to cancel out the pulse shift which would otherwise appear when the particular pattern is recorded and suBsequently retrieved.
Claim 5
Dependent Claim 92 words
The compensation system of claim 1 wherein said pulse means shifting means comprises: means, responsive to the detection of the first particular pattern of stored pulses, for advancing a pulse within the first particular pattern of stored pulses by a defined amount relative to the time in which it would otherwise occur; and means, responsive to the detection of the second particular pattern of stored pulses, for delaying a pulse within the second particular pattern of stored pulses by a defined amount relative to the time in which it would otherwise occur.
Claim 6
Dependent Claim 78 words
The compensation system of claim 2 further comprising: means for generating and advanced clock signal, and a delayed clock signal; and wherein said means for advancing a pulse within the firt particular pattern comprises first means for gating the pulse to be advanced with the advanced clock signal; and said means, for delaying a pulse within the second particular pattern of stored pulses comprises second means for gating the pulse to be delayed with the delayed clock signal.
Claim 7
Dependent Claim 104 words
The compensation system of claim 1 wherein the first pattern of pulses consists of a first occurring pulse followed by a second occurring pulse spaced one full bit cell from the first occurring pulse and said second occurrring pulse is followed by the absence of another pulse for at least one and one-half bit cells, and wherein the second pattern of pulses comprises a first occurring pulse which has been immediately preceded by the absence of any pulse for one and one-half bit cells and which is followed by a second pulse which is spaced one full bit cell from the first occurring pulse.
Claim 8
Dependent Claim 91 words
The compensation system of claim 4 wherein said pulse shifting means comprises: means, responsive to the detection of the first particular pattern of stored pulses, for advancing a pulse within the first particular pattern of stored pulses by a defined amount relative to the time in which it would otherwise occur; and means, responsive to the detection of the second particular pattern of stored pulses, for delaying a pulse within the second particular pattern of stored pulses by a defined amount relative to the time in which it would otherwise occur.
Claim 9
Dependent Claim 78 words
The compensation system of claim 5 further comprising: means for generating an advanced clock signal, and a delayed clock signal; and wherein said means for advancing a pulse within the first particular pattern comprises first means for gating the pulse to be advanced with the advanced clock signal; and said means, for delaying a pulse within the second particular pattern of stored pulses comprises second means for gating the pulse to be delayed with the delayed clock signal.
Claim 10
Dependent Claim 48 words
The recording system of claim 6 further comprising: a write drive circuit for recording the shifted pulses from said pulse shift means; fault detection means for detecting an erroneous shift command signal from said decoding means, said detection means generating an error signal to said write driver circuit.
Claim 11
Dependent Claim 48 words
The recording system of claim 3 further comprising: a write drive circuit for recording the shifted pulses from said pulse shift means; fault detection means for detecting an erroneous shift command signal from said decoding means, said detection means generating an error signal to said write driver circuit.
Claim 12
Dependent Claim 94 words
The compensation system of claim 8 wherein said decoding, means generates three separate shift commands to said pulse shifting means, an advance shift command when the first particular pattern of pulses is detected, a delay shift command when the second particular pattern of pulses is detected, and no-shift command when any other pattern of pulses is detected, and said fault detection means comprises: means for determining when the three separate shift commands are all logically low, and means for determining when two or more of the three separate shift commands are all logically high.
Claim 13
Dependent Claim 95 words
The compensation system of claim 7 wherein said decoding means generates three separate shift commands to said pulse shifting means, an advance shift command when the first particular pattern of pulses is detected, a delay shift command when the second particular pattern of pulses is detected, and a no-shift command when any other pattern of pulses is detected, and said fault detection means comprises: means for determining when the three separate shift commands are all logically low, and means for determining when two or more of the three separate shift commands are all logically high.
Claim 14
Dependent Claim 174 words
A digital data compensation system which compensates for pulse shifting occurring in a pulse encoded signal comprising a series of bit cells wherein the leading edge of a pulse occurs at the middle of a binary one encoded bit cell and occurs at the junction between successive binary zero encoded bit cells, when the pulse encoded signal is recorded and subsequently retrieved from a magnetic medium said system comprising: a plurality of at least six serially connected bilevel storage means for temporarily storing a plurality of equally segmented one-half bit cell portions of the pulse encoded signal, each bilevel storage means being operative to produce a bilevel signal indicative of the particularly stored segmented portion; means for decoding the bilevel signals from said plurality of bilevel storage means, said decoding means comprising means for generating pulse shift command signals in response to the signal conditions of the bilevel signals from said plurality of bilevel storage means; and means for selectively shifting pulses from the pulse encoded signal in response to the pulse shift commands.
Claim 15
Dependent Claim 174 words
A digital data compensation system which compensates for pulse shifting occurring in a pulse encoded signal comprising a series of bit cells wherein the leading edge of a pulse occurs at the middle of a binary one encoded bit cell and occurs at the junction between successive binary zero encoded bit cells, when the pulse encoded signal is recorded and subsequently retrieved from a magnetic medium said system comprising: a plurality of at least six serially connected bilevel storage means for temporarily storing a plurality of equally segmented one-half bit cell portions of the pulse encoded signal, each bilevel storage means being operative to produce a bilevel signal indicative of the particularly stored segmented portion; means for decoding the bilevel signals from said plurality of bilevel storage means, said decoding means comprising means for generating pulse shift command signals in response to the signal conditions of the bilevel signals from said plurality of bilevel storage means; and means for selectively shifting pulses from the pulse encoded signal in response to the pulse shift commands.
Claim 16
Dependent Claim 49 words
The digital data compensation system of claim 11 wherein said means for generating pulse shift command signals comprises: means responsive to a first pattern of bilevel signals for generating an advance shift command, and means responsive to a second pattern of bilevel signals for generating a delay shift command.
Claim 17
Dependent Claim 73 words
The digital data compensation system of claim 12 wherein said plurality of at least six bilevel storage means comprises in numerically ascending order six edge triggered flip-flops each of which is triggered so as to store one-half of a bit cell of the pulse encoded signal at a time with the first, lowest ordered, edge triggered flip-flop storing the latest of the so stored one-half bit cell periods of the pulse encoded signal.
Claim 18
Dependent Claim 74 words
The digital data compensation system of claim 13 wherein the first pattern of bilevel signals is generated when the fourth and sixth edge triggered flip-flops are logically high and the second, third and fifth edge triggered flip-flops are logically low; and wherein the second pattern of bilevel signals is generated when the second and fourth edge triggered flip-flops are logically high and the first, third, fifth and sixth edge triggered flip-flops are logically low.
Claim 19
Dependent Claim 28 words
The digital data compensation system of claim 14 wherein the bilevel output signal of the fourth edge triggered flip-flop is applied to said means for selectively shifting pulses.
Claim 20
Dependent Claim 57 words
The digital data compensation system of claim 15 wherein said means for selectively shifting pulses comprises: means for advancing the bilevel output signal from the fourth edge triggered flip-flop in response to an advance shift command; and means for delaying the bilevel output signal from the fourth edge triggered flip-flop in response to a delay shift command.

References Cited (Backward Citations)

US3067422A Cited
US3159840A Cited
US3345638A Cited
US3377583A Cited
US3488662A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-04-21 1978-10-21 1979-04-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-04-21 1982-10-21 1983-04-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-04-21 1986-10-21 1987-04-22 $7700.00 Window Closed / Lapsed

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