Television signal processing unit which provides monitoring during periods of the television signal to detect erroneous circuit operation

Claim 2

A processing unit for processing a supplied television signal representing successive frames of a television picture, said processing unit comprising: at least one circuit section for processing an input signal supplied thereto which has been derived from said television signal by one or more other circuit sections of said processing unit; a test signal generator coupled to the input of said one circuit section for supplying a test signal thereto during allocated periods of the television signal, each allocated period being during a portion of a picture frame during which video information is not present, said one circuit section producing from the supplied test signal a processed test signal at an output thereof; an evaluation circuit coupled to the output of said one circuit section for comparing the processed test signal with a predetermined specimen signal corresponding to a correct processing of the supplied test signal by said one circuit section, and for producing an error indication when the processed test signal differs from the specimen signal; and said test signal generator comprising: an analysis circuit for selecting said allocated periods of the television signal; an address counter controlled by the analysis circuit to produce address counts which begin and end concurrently with the beginning and end of each of said allocated periods of television signal; a memory having address locations for storing therein respective samples of said test signal, the stored test signal samples being supplied from said memory in response to the address counts produced by said address counter; and switching means coupled to said memory and controlled by said analysis circuit to switch the input of said one circuit section so as to receive test signal samples supplied by said memory during said allocated periods of the television signal and to receive said input signal during other periods of the television signal.

Claim 3

A processing circuit as claimed in claim 1, wherein the analysis circuit comprises a period counter for counting successive allocated periods of the television signal, and a decoding circuit for evaluating the count of the period counter and based thereon generating control signals for said address counter and said switching means.

Claim 4

A processing circuit as claimed in claim 2, wherein the analysis circuit selects as allocated periods of the television signal periods thereof which are not assigned to video information.

Claim 5

A processing circuit as claimed in claim 3, wherein the analysis circuit further selects as allocated periods of the television signal periods thereof which are assigned to video information but wherein no video information is present.

Claim 6

A processing unit for processing a supplied television signal representing successive frames of a television picture, said processing unit comprising: at least one circuit section for processing an input signal supplied thereto which has been derived from said television signal by one or more other circuit sections of said processing unit; a test signal generator coupled to the input of said one circuit section for supplying a test signal thereto during allocated periods of the television signal, each allocated period being during a portion of a picture frame during which video information is not present, said one circuit section producing from the supplied test signal a processed test signal at an output thereof; an evaluation circuit coupled to the output of said one circuit section for comparing the processed test signal with a predetermined specimen signal corresponding to a correct processing of the supplied test signal by said one circuit section, and for producing an error indication when the processed test signal differs from the specimen signal; and said evaluation circuit comprising: an analysis circuit for detecting the allocated periods of the television signal during which a test signal is supplied to said one circuit section; an address counter controlled by the analysis circuit to produce address counts which begin and end concurrently with the beginning and end of each of said allocated periods of the television signal; a memory having address locations for storing therein respective samples of said specimen signal, the stored samples being supplied from said memory in response to the address counts produced said address counter; and a comparison circuit coupled to said memory and controlled by said analysis circuit to compare the specimen signal samples supplied by said memory with samples of the processed test signal produced by said one circuit section, and produce said error indication when the processed test signal samples differ from the specimen signal samples.

Claim 7

A processing unit for processing a supplied television signal representing successive frames of a television picture, said processing unit comprising: at least one circuit section for processing an input signal supplied thereto which has been derived from said television signal by one or more other circuit sections of said processing unit; a test signal generator coupled to the input of said one circuit section for supplying a test signal thereto during allocated periods of the television signal, each allocated period being during a portion of a picture frame during which video information is not present, said one circuit section producing from the supplied test signal a processed test signal at an output thereof; an evaluation circuit coupled to the output of said one circuit section for comparing the processed test signal with a predetermined specimen signal corresponding to a correct processing of the supplied test signal by said one circuit section, and for producing an error indication when the processed test signal differs from the specimen signal; and said evaluation circuit comprising: an analysis circuit for detecting the allocated periods of the television signal during which a test signal is supplied to said one circuit section; an address counter controlled by the analysis circuit to produce address counts which begin and end concurrently with the beginning and end of each of said allocated periods of the television signal; a memory having address locations for storing therein respective samples of said specimen signal, the stored samples being supplied from said memory in response to the address counts produced said address counter; and a comparison circuit coupled to said memory and controlled by said analysis circuit to compare the specimen signal samples supplied by said memory with samples of the processed test signal produced by said one circuit section, and produce said error indication when the processed test signal samples differ from the specimen signal samples.

Claim 8

A processing circuit as claimed in claim 5, wherein said analysis circuit comprises a period counter for counting successive allocated periods of the television signal, and a decoding circuit for evaluation the count of the period counter and based thereon producing control signals for said address counter and said comparison circuit.

Claim 9

A processing circuit as claimed in claim 6, wherein the analysis circuit detects allocated periods of the television signal which are not assigned to video information.

Claim 10

A processing circuit as claimed in claim 7, wherein the analysis circuit further detects allocated periods of the television signal which are assigned to video information but wherein no video information is present.