US5323048A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MIS type semiconductor ROM programmed by conductive interconnects
Assignee: Panasonic Holdings Corp
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Filing: 1993-09-10
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Granted: 1994-06-21
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Expires: 2013-09-10
Abstract
Abstract An MIS device which includes a source diffusion layer and a drain diffusion layer under the surface of a semiconductor substrate, and a plurality of gate insulation films on the surface of the semiconductor substrate. Further, a plurality of gate electrodes are formed on the plurality of gate insulation films in series with one another between the source diffusion layer and the drain diffusion layer. Moreover, inter-gate-electrode diffusion layers are formed under the surfaces of regions of the semiconductor substrate among the plurality of the gate electrodes. Insulating side walls are provided on both sides of each of the gate electrodes. Furthermore, conductive layers are provided, each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes and covering the insulating side walls provided on that one inter-gate-electrode diffusion layer, and filling a depression surrounded by the insulating side walls and that one inter-gate-electrode diffusion layers. An insulation layer covers the gate electrodes and the conductive layers, at least partly. A conductive wiring layer on the insulation layer is in contact with a part of the conductive layer, which is not covered by the insulation layer. The conductive layers at both sides of at least one of the gate electrodes are selectively interconnected on that gate electrode. Thus at least one of the inter-gate-electrode diffusion layers provided among the plurality of the gate electrodes, which are used in a memory cell, is covered by a conductive layer. As the result, the transconductance of an enhancement type transistor can be increased. An amplification factor and a switching speed of the enhancement type transistor can be improved. Consequently, a high-speed operation can stably be performed.
Inventors
- 👤 Makoto Onuma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:22
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/30; H10B20/34; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/84
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
316 words
A semiconductor device having a source diffusion layer and a drain diffusion layer formed under a surface of a semiconductor substrate, a plurality of gate insulation films formed on the surface of the semiconductor substrate, a plurality of memory-cell transistor gate electrodes and two or more selection line transistor gate electrodes, which are formed on the plurality of gate insulation films in such a manner to be arranged in series with one another between the source diffusion layer, inter-gate-electrode diffusion layers formed under surfaces of regions of the semiconductor substrate among the plurality of the memory-cell transistor gate electrodes and the two or more selection line transistor gate electrodes, insulating side walls provided on both sides of each of the gate electrodes, conductive material layers each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes arranged in series with one another and covering the insulating side walls provided on said at least one of the inter-gate-electrode diffusion layers and filling a depression surrounded by the insulating side walls and said at least one of the inter-gate-electrode diffusion layers, an insulation layer for covering the gate electrodes and for covering the conductive material layers partly, and a conductive wiring layer provided on the insulation layer and in contact with a part of the conductive material layer, which part is not covered by the insulation layer, wherein the conductive material layers provided at both sides of at least one of the plurality of the gate electrodes are selectively interconnected on at least one of the plurality of the gate electrodes, wherein one of the inter-gate-electrode diffusion layers, which is provided among the two or more selection line transistor gate electrodes, is connected to the conductive material layer which covers the one of the inter-gate-electrode diffusion layers and is connected to at least one of the source and drain diffusion layers.
Claim 2
Dependent Claim
316 words
A semiconductor device having a source diffusion layer and a drain diffusion layer formed under a surface of a semiconductor substrate, a plurality of gate insulation films formed on the surface of the semiconductor substrate, a plurality of memory-cell transistor gate electrodes and two or more selection line transistor gate electrodes, which are formed on the plurality of gate insulation films in such a manner to be arranged in series with one another between the source diffusion layer, inter-gate-electrode diffusion layers formed under surfaces of regions of the semiconductor substrate among the plurality of the memory-cell transistor gate electrodes and the two or more selection line transistor gate electrodes, insulating side walls provided on both sides of each of the gate electrodes, conductive material layers each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes arranged in series with one another and covering the insulating side walls provided on said at least one of the inter-gate-electrode diffusion layers and filling a depression surrounded by the insulating side walls and said at least one of the inter-gate-electrode diffusion layers, an insulation layer for covering the gate electrodes and for covering the conductive material layers partly, and a conductive wiring layer provided on the insulation layer and in contact with a part of the conductive material layer, which part is not covered by the insulation layer, wherein the conductive material layers provided at both sides of at least one of the plurality of the gate electrodes are selectively interconnected on at least one of the plurality of the gate electrodes, wherein one of the inter-gate-electrode diffusion layers, which is provided among the two or more selection line transistor gate electrodes, is connected to the conductive material layer which covers the one of the inter-gate-electrode diffusion layers and is connected to at least one of the source and drain diffusion layers.
Claim 3
Dependent Claim
465 words
A semiconductor device having a source diffusion layer and a drain diffusion layer formed under a surface of a semiconductor substrate, a plurality of gate insulation films formed on the surface of the semiconductor substrate, a plurality of memory-cell transistor gate electrodes and two or more selection line transistor gate electrodes, which are formed on the plurality of gate insulation films in such a manner to be arranged in series with one another between the source and drain diffusion layers, inter-gate-electrode diffusion layers formed under surfaces of regions of the semiconductor substrate among the plurality of the memory-cell transistor gate electrodes and the two or more selection line transistor gate electrodes, insulating side walls provided on both sides of each of the gate electrodes, conductive material layers each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes arranged in series with one another and covering the insulating side walls provided on said at least one of the inter-gate-electrode diffusion layers and filling a depression surrounded by the insulating side walls and said at least one of the inter-gate-electrode diffusion layers, an insulation layer for covering the gate electrodes and for covering the conductive material layers partly, and a conductive wiring layer provided on the insulation layer and in contact with a part of the conductive material layer, which part is not covered by the insulation layer, wherein the conductive material layers provided at both sides of at least one of the plurality of the gate electrodes are selectively interconnected on at least one of the plurality of the gate electrodes, wherein the diffusion layers placed at both sides of the selection line transistor gate electrode corresponding to a selection line transistor serving as a depletion type transistor among a plurality of memory-cell transistors, each of which is comprised of the source diffusion layer, the drain diffusion layer, the inter-gate-electrode diffusion layer, the plurality of memory-cell transistor gate electrodes and the two or more selection line transistor gate electrodes, and two or more selection line transistors are covered by the conductive material layers, wherein the conductive material layers are connected to each other on the selection line transistor gate electrode corresponding to the selection line transistor serving as a depletion type transistor, and wherein portions corresponding to two depletion type transistors used as the selection line transistors, between which the source or drain diffusion layer is inserted, are aligned in the direction along which a bit line extends, wherein one of the inter-gate-electrode diffusion layers, which is provided among the two or more selection line transistor gate electrodes, is connected to the conductive material layer which covers the one of the inter-gate-electrode diffusion layers and is connected to at least one of the source and drain diffusion layers.
Claim 4
Dependent Claim
465 words
A semiconductor device having a source diffusion layer and a drain diffusion layer formed under a surface of a semiconductor substrate, a plurality of gate insulation films formed on the surface of the semiconductor substrate, a plurality of memory-cell transistor gate electrodes and two or more selection line transistor gate electrodes, which are formed on the plurality of gate insulation films in such a manner to be arranged in series with one another between the source and drain diffusion layers, inter-gate-electrode diffusion layers formed under surfaces of regions of the semiconductor substrate among the plurality of the memory-cell transistor gate electrodes and the two or more selection line transistor gate electrodes, insulating side walls provided on both sides of each of the gate electrodes, conductive material layers each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes arranged in series with one another and covering the insulating side walls provided on said at least one of the inter-gate-electrode diffusion layers and filling a depression surrounded by the insulating side walls and said at least one of the inter-gate-electrode diffusion layers, an insulation layer for covering the gate electrodes and for covering the conductive material layers partly, and a conductive wiring layer provided on the insulation layer and in contact with a part of the conductive material layer, which part is not covered by the insulation layer, wherein the conductive material layers provided at both sides of at least one of the plurality of the gate electrodes are selectively interconnected on at least one of the plurality of the gate electrodes, wherein the diffusion layers placed at both sides of the selection line transistor gate electrode corresponding to a selection line transistor serving as a depletion type transistor among a plurality of memory-cell transistors, each of which is comprised of the source diffusion layer, the drain diffusion layer, the inter-gate-electrode diffusion layer, the plurality of memory-cell transistor gate electrodes and the two or more selection line transistor gate electrodes, and two or more selection line transistors are covered by the conductive material layers, wherein the conductive material layers are connected to each other on the selection line transistor gate electrode corresponding to the selection line transistor serving as a depletion type transistor, and wherein portions corresponding to two depletion type transistors used as the selection line transistors, between which the source or drain diffusion layer is inserted, are aligned in the direction along which a bit line extends, wherein one of the inter-gate-electrode diffusion layers, which is provided among the two or more selection line transistor gate electrodes, is connected to the conductive material layer which covers the one of the inter-gate-electrode diffusion layers and is connected to at least one of the source and drain diffusion layers.
Claim 5
Dependent Claim
458 words
A semiconductor device having a source diffusion layer and a drain diffusion layer formed under a surface of a semiconductor substrate, a plurality of gate insulation films formed on the surface of the semiconductor substrate, a plurality of memory-cell transistor gate electrodes formed on the plurality of gate insulation films in such a manner to be arranged in series with one another between the source and drain diffusion layers, inter-gate-electrode diffusion layers formed under surfaces of regions of the semiconductor substrate among the plurality of the memory-cell transistor gate electrodes, insulating sidewalls provided on both sides of each of the gate electrodes, conductive material layers each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes arranged in series with one another and covering the insulating side walls provided on said at least one of the inter-gate-electrode diffusion layers and filling a depression surrounded by the insulating side walls and said at least one of the inter-gate-electrode diffusion layers, an insulation layer for covering the gate electrodes and for covering the conductive material layers partly, and a conductive wiring layer provided on the insulation layer and in contact with a part of the conductive material layer, which part is not covered by the insulation layer, wherein one of the inter-gate-electrode diffusion layers, which is provided among the two or more selection line transistor gate electrodes, is connected to the conductive material layer which covers the one of the inter-gate-electrode diffusion layers and is connected to at least one of the source and drain diffusion layers, wherein the conductive material layers provided at both sides of at least one of the plurality of the gate electrodes are selectively interconnected on at least one of the plurality of the gate electrodes, wherein among a plurality of memory-cell transistors, each of which is comprised of the source region, the drain region, the inter-gate-electrode diffusion layer and the plurality of the memory-cell transistor gate electrodes, a memory-cell transistor serves as a depletion type transistor correspondingly to a program employed for a read-only memory, wherein the diffusion layers placed at both sides of the memory-cell transistor gate electrode corresponding to the memory-cell transistor serving as the depletion type transistor are covered by the conductive material layers used for writing a program to a contact portion of the substrate corresponding to the source or drain diffusion layer, wherein the conductive material layers used for writing a program thereto are connected to each other on the memory-cell transistor gate electrode corresponding to the memory-cell transistor serving as the depletion type transistor, and wherein the conductive material layer used for writing a program to the contact portion is formed on the contact portion and is employed as a spacer.
Claim 6
Dependent Claim
458 words
A semiconductor device having a source diffusion layer and a drain diffusion layer formed under a surface of a semiconductor substrate, a plurality of gate insulation films formed on the surface of the semiconductor substrate, a plurality of memory-cell transistor gate electrodes formed on the plurality of gate insulation films in such a manner to be arranged in series with one another between the source and drain diffusion layers, inter-gate-electrode diffusion layers formed under surfaces of regions of the semiconductor substrate among the plurality of the memory-cell transistor gate electrodes, insulating sidewalls provided on both sides of each of the gate electrodes, conductive material layers each for covering at least one of the inter-gate-electrode diffusion layers among the plurality of the gate electrodes arranged in series with one another and covering the insulating side walls provided on said at least one of the inter-gate-electrode diffusion layers and filling a depression surrounded by the insulating side walls and said at least one of the inter-gate-electrode diffusion layers, an insulation layer for covering the gate electrodes and for covering the conductive material layers partly, and a conductive wiring layer provided on the insulation layer and in contact with a part of the conductive material layer, which part is not covered by the insulation layer, wherein one of the inter-gate-electrode diffusion layers, which is provided among the two or more selection line transistor gate electrodes, is connected to the conductive material layer which covers the one of the inter-gate-electrode diffusion layers and is connected to at least one of the source and drain diffusion layers, wherein the conductive material layers provided at both sides of at least one of the plurality of the gate electrodes are selectively interconnected on at least one of the plurality of the gate electrodes, wherein among a plurality of memory-cell transistors, each of which is comprised of the source region, the drain region, the inter-gate-electrode diffusion layer and the plurality of the memory-cell transistor gate electrodes, a memory-cell transistor serves as a depletion type transistor correspondingly to a program employed for a read-only memory, wherein the diffusion layers placed at both sides of the memory-cell transistor gate electrode corresponding to the memory-cell transistor serving as the depletion type transistor are covered by the conductive material layers used for writing a program to a contact portion of the substrate corresponding to the source or drain diffusion layer, wherein the conductive material layers used for writing a program thereto are connected to each other on the memory-cell transistor gate electrode corresponding to the memory-cell transistor serving as the depletion type transistor, and wherein the conductive material layer used for writing a program to the contact portion is formed on the contact portion and is employed as a spacer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-20 | 1997-12-20 | 1998-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-20 | 2001-12-20 | 2002-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-20 | 2005-12-20 | 2006-06-21 | $7700.00 | Window Closed / Lapsed |