Semiconductor integrated circuit device having various blocks specifically arranged on a single semiconductor substrate for high speed operation

Claim 2

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: an input stage for receiving a first input signal and delivering at one timing a second input signal corresponding to said first input signal; a plurality of function blocks each electrically connected with said input stage to operate in parallel to generate an output signal responsive to said second input signal and at a plurality of different timings; an output stage electrically connected with said function blocks to receive the output signal of said each function block for producing a device output signal; said input stage, said function blocks and said output stage being in an arrangement on said signal semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device, and said function blocks being set in operation with different timing in accordance with said arrangement as caused by different propagation delays for said second input signal; and said arrangement being such that a sum of a first period of time taken for said second input signal propagating from said input stage to reach one function block and a second period of time taken for the output signal of said one function block propagating therefrom to said output stage is substantially the same for all of said plurality of function blocks.

Claim 3

A semiconductor integrated circuit device of claim 1, wherein: the input stage is an input buffer for converting a first address signal as the first input signal to a second address signal as the second input signal; the function blocks are a plurality of memory blocks each electrically connected with said input buffer so that each of the function blocks delivers an output signal responsive to said second address signal; and the output stage is a logic circuit.

Claim 4

A semiconductor integrated circuit device of claim 2, further comprising: at least one internal amplifier for amplifying said second address signal; and said input buffer, said memory blocks, said at least one internal amplifier and said logic circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device, said memory blocks being set in operation with different timing in accordance with said arrangement order, and said at least one internal amplifier being connected to supply said amplified second address signal to any of those of said memory blocks which are preceded by said internal amplifier as viewed in the direction of said progress of signal processing operations in the integrated circuit device so that said memory blocks preceded by said internal amplifier are connected with said input buffer through said internal amplifier.

Claim 5

A semiconductor integrated circuit device of claim 3, further comprising: a first latch circuit for receiving a first address signal, and delivering said first address signal with a first timing to said input buffer; a second latch circuit for receiving said device output signal and delivering said device output signal with a second timing; and said first latch circuit, said input buffer, said memory blocks, said at least one internal amplifier, said logic circuit and said second latch circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device.

Claim 6

A semiconductor integrated circuit device of claim 4, wherein said arrangement is such that some of said function blocks are located a greater distance from said input stage than others of said function blocks; and further including a plurality of internal repeating amplifiers between said some function blocks and said input stage for amplifying said second input signal and said others of said function blocks being electrically connected with said input stage for transferring said second input signal without amplification.

Claim 7

A semiconductor integrated circuit device of claim 4, further including delay gates for delaying signal propagation only with respect to some of said function blocks to equalize the first period of time and the second period of time.

Claim 8

A semiconductor integrated circuit device of claim 3, further including delay gates for delaying signal propagation only with respect to some of said function blocks to equalize the first period of time and the second period of time.

Claim 9

A semiconductor integrated circuit device of claim 3, wherein said arrangement is such that some of said function blocks are located a greater distance from said input stage than others of said function blocks; and further including a plurality of internal repeating amplifiers between said some function blocks and said input stage for amplifying said second input signal and said others of said function blocks being electrically connected with said input stage for transferring said second input signal without amplification.

Claim 10

A semiconductor integrated circuit device of claim 2, further including delay gates for delaying signal propagation only with respect to some of said function blocks to equalize the first period of time and the second period of time.

Claim 11

A semiconductor integrated circuit device of claim 2, wherein said arrangement is such that some of said function blocks are located a greater distance from said input stage than others of said function blocks; and further including a plurality of internal repeating amplifiers between said some function blocks and said input stage for amplifying said second input signal and said others of said function blocks being electrically connected with said input stage for transferring said second input signal without amplification.

Claim 12

A semiconductor integrated circuit device of claim 1, further including delay gates for delaying signal propagation only with respect to some of said function blocks to equalize the first period of time and the second period of time.

Claim 13

A semiconductor integrated circuit device of claim 1, wherein said arrangement is such that some of said function blocks are located a greater distance from said input stage than others of said function blocks; and further including a plurality of internal repeating amplifiers between said some function blocks and said input stage for amplifying said second input signal and said others of said function blocks being electrically connected with said input stage for transferring said second input signal without amplification.

Claim 14

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: an input stage for receiving a first input signal and delivering a second input signal corresponding to said first input signal; a plurality of function blocks each electrically connected with said input stage to operate to generate an output signal responsive to said second input signal; an output stage electrically connected with said function blocks to receive the output signal of said each function block for producing a device output signal, said input stage, said function blocks and said output stage being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device; and the length of a conductor for the electrical connection of any one of said function blocks with said input stage is smaller than that for the electrical connection of another one of said function blocks with said input stage, said another function block being generally located more distant from said input stage than said one function block on said single substrate so that said function blocks are brought into operation responsive to said second input signal in the ascending order of the lengths of the conductors for the electrical connection of said input stage with said function blocks.

Claim 15

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: an input stage for receiving a first input signal and delivering a second input signal corresponding to said first input signal; a plurality of function blocks each electrically connected with said input stage to operate to generate an output signal responsive to said second input signal; an output stage electrically connected with said function blocks to receive the output signal of said each function block for producing a device output signal, said input stage, said function blocks and said output stage being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device; and the length of a conductor for the electrical connection of any one of said function blocks with said input stage is smaller than that for the electrical connection of another one of said function blocks with said input stage, said another function block being generally located more distant from said input stage than said one function block on said single substrate so that said function blocks are brought into operation responsive to said second input signal in the ascending order of the lengths of the conductors for the electrical connection of said input stage with said function blocks.

Claim 16

A semiconductor integrated circuit device according to claim 13, in which the length of a conductor for the electrical connection of said one function block with said output stage is larger than that for the electrical connection of said another function block with said output stage, said one function block being generally more distant from said output stage than said another function block on said single substrate so that a time necessary for the output signal generated by said one function block to propagate on the conductor to reach said output stage is longer than that for the output signal generated by said another function block.

Claim 17

A semiconductor integrated circuit device according to claim 13, wherein some of said function blocks are located a greater distance from said input stage than others of said function blocks; and further including a plurality of internal repeating amplifiers between said some function blocks and said input stage for amplifying said second input signal and said others of said function blocks being electrically connected with said input stage for transferring said second input signal without amplification.

Claim 18

A semiconductor memory device formed with a single semiconductor substrate, comprising: an input buffer for converting a first address signal to a second address signal; a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; a logic circuit electrically connected with said memory blocks to receive the output signal of said each memory block for producing a device output signal, said input buffer, said memory blocks and said logic circuit being arranged on said single semiconductor substrate in a progressing order of signal processing operations to be performed in the semiconductor memory device; the length of a conductor for the electrical connection of any one of said memory blocks with said input buffer is smaller than that for the electrical connection of another one of said memory blocks with said input buffer, said another memory block being generally located more distant from said input buffer than said one memory block on said single substrate so that said memory blocks are brought into operation responsive to said second address signal in the ascending order of the lengths of the conductors for the electrical connection of said input buffer with said memory blocks; and the length of a conductor for the electrical connection of said one memory block with said logic circuit is larger than that for the electrical connection of said another memory block with said logic circuit, said one memory block being generally more distant from said logic circuit than said another memory block on said single substrate so that a time necessary for the output signal generated by said one memory block to propagate on the conductor to reach said logic circuit is longer than that for the output signal generated by said another memory block does, whereby a sum of a first period of time taken for said second address signal propagating from said input buffer to reach one memory block and a second period of time taken for the output signal of said one memory block propagating therefrom to said logic circuit is substantially the same for all of said plurality of memory blocks.

Claim 19

A semiconductor memory device formed with a single semiconductor substrate, comprising: an input buffer for converting a first address signal to a second address signal; a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; a logic circuit electrically connected with said memory blocks to receive the output signal of said each memory block for producing a device output signal, said input buffer, said memory blocks and said logic circuit being arranged on said single semiconductor substrate in a progressing order of signal processing operations to be performed in the semiconductor memory device; the length of a conductor for the electrical connection of any one of said memory blocks with said input buffer is smaller than that for the electrical connection of another one of said memory blocks with said input buffer, said another memory block being generally located more distant from said input buffer than said one memory block on said single substrate so that said memory blocks are brought into operation responsive to said second address signal in the ascending order of the lengths of the conductors for the electrical connection of said input buffer with said memory blocks; and the length of a conductor for the electrical connection of said one memory block with said logic circuit is larger than that for the electrical connection of said another memory block with said logic circuit, said one memory block being generally more distant from said logic circuit than said another memory block on said single substrate so that a time necessary for the output signal generated by said one memory block to propagate on the conductor to reach said logic circuit is longer than that for the output signal generated by said another memory block does, whereby a sum of a first period of time taken for said second address signal propagating from said input buffer to reach one memory block and a second period of time taken for the output signal of said one memory block propagating therefrom to said logic circuit is substantially the same for all of said plurality of memory blocks.

Claim 20

A semiconductor memory device of claim 16, wherein some of said memory blocks are located a greater distance from said input buffer than others of said function blocks; and further including a plurality of internal repeating amplifiers between said some function blocks and said input buffer for amplifying said second address signal and said others of said function blocks being electrically connected with said input buffer for transferring said second address signal without amplification.

Claim 21

A semiconductor memory device formed with a single semiconductor substrate, comprising: an input buffer for converting a first address signal to a second address signal; a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; at least one internal amplifier for amplifying said second address signal; a logic circuit electrically connected with said memory blocks to receive the output signal of said each memory block for producing a device output signal, said input buffer, said memory blocks, said at least one internal amplifier and said logic circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor memory device, and said at least one internal amplifier being connected to supply said amplified second address signal to any of those of said memory blocks preceded by said internal amplifier as viewed in the direction of said internal amplifier as viewed in the direction of said progress of signal processing operations in the memory device so that said memory blocks preceded by said internal amplifier are connected with said input buffer through said internal amplifier; the length of a conductor for the electrical connection of any one of said memory blocks with said input buffer is smaller than that for the electrical connection of another one of said memory blocks with said input buffer, said another memory block being generally located more distant from said input buffer than said one memory block on said single substrate so that said memory blocks are brought into operation responsive to said second input signal in the ascending order of the lengths of the conductors for the electrical connection of said input buffer with said memory blocks; and the length of a conductor for the electrical connection of said one memory block with said logic circuit is larger than that for the electrical connection of said another memory block with said logic circuit, said one memory block being generally more distant from said logic circuit than said another memory block on said single substrate so that a time necessary for the output signal generated by said one memory block to propagate on the conductor to reach said logic circuit is longer than that for the output signal generated by said another memory block, whereby a sum of a first period of time taken for said second address signal propagating from said input buffer to reach one memory block and a second period of time taken for the output signal of said one memory block propagating therefrom to said logic circuit is substantially the same for all of said plurality of memory blocks.

Claim 22

A semiconductor memory device formed with a single semiconductor substrate, comprising: an input buffer for converting a first address signal to a second address signal; a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; at least one internal amplifier for amplifying said second address signal; a logic circuit electrically connected with said memory blocks to receive the output signal of said each memory block for producing a device output signal, said input buffer, said memory blocks, said at least one internal amplifier and said logic circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor memory device, and said at least one internal amplifier being connected to supply said amplified second address signal to any of those of said memory blocks preceded by said internal amplifier as viewed in the direction of said internal amplifier as viewed in the direction of said progress of signal processing operations in the memory device so that said memory blocks preceded by said internal amplifier are connected with said input buffer through said internal amplifier; the length of a conductor for the electrical connection of any one of said memory blocks with said input buffer is smaller than that for the electrical connection of another one of said memory blocks with said input buffer, said another memory block being generally located more distant from said input buffer than said one memory block on said single substrate so that said memory blocks are brought into operation responsive to said second input signal in the ascending order of the lengths of the conductors for the electrical connection of said input buffer with said memory blocks; and the length of a conductor for the electrical connection of said one memory block with said logic circuit is larger than that for the electrical connection of said another memory block with said logic circuit, said one memory block being generally more distant from said logic circuit than said another memory block on said single substrate so that a time necessary for the output signal generated by said one memory block to propagate on the conductor to reach said logic circuit is longer than that for the output signal generated by said another memory block, whereby a sum of a first period of time taken for said second address signal propagating from said input buffer to reach one memory block and a second period of time taken for the output signal of said one memory block propagating therefrom to said logic circuit is substantially the same for all of said plurality of memory blocks.

Claim 23

A semiconductor memory device according to claim 18, in which said logic circuit is an output data selecting circuit for selectively transferring the output signal of at least one of said plurality of memory blocks as said device output signal.

Claim 24

A semiconductor memory device according to claim 18, wherein some of said memory blocks are located a greater distance from said input buffer than others of said memory blocks; and further including a plurality of internal repeating amplifiers between said some memory blocks and said input buffer for amplifying said second address signal and said others of said memory blocks being electrically connected with said input buffer for transferring said second address signal without amplification.

Claim 25

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: a first latch circuit for receiving a first address signal, and delivering said first address signal with a first timing; an input buffer for receiving said first address signal from said first latch circuit and converting said first address signal to a second address signal; a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; at least one internal amplifier for amplifying said second address signal; a logic circuit electrically connected with said memory blocks to receive the output signal of said each memory block for producing a device output signal; and a second latch circuit for receiving said device output signal and delivering said device output signal with a second timing, said first latch circuit, said input buffer, said memory blocks, said at least one internal amplifier, said logic circuit and said second latch circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device, and said at least one internal amplifier being connected to supply said amplified second address signal to any of those of said memory blocks preceded by said internal amplifier as viewed in the direction of said progress of signal processing operations in the integrated circuit device so that said memory blocks preceded by said internal amplifier are connected with said input buffer through said internal amplifier; the length of a conductor for the electrical connection of any one of said memory blocks with said input buffer is smaller than that for the electrical connection of another one of said memory blocks with said input buffer, said another memory block being generally located more distant from said input buffer than said one memory block on said single substrate so that said memory blocks are brought into operation responsive to said second address signal in the ascending order of the lengths of the conductors for the electrical connection of said input buffer with said memory blocks; and the length of a conductor for the electrical connection of said one memory block with said logic circuit is larger than that for the electrical connection of said another memory block with said logic circuit, said one memory block being generally more distant from said logic circuit than said another memory block on said single substrate so that a time necessary for the output signal generated by said one memory block to propagate on the conductor to reach said logic circuit is longer than that for the output signal generated by said another memory block, whereby a sum of a first period of time taken for said second address signal propagating from said input buffer to reach one memory block and a second period of time taken for the output signal of said one memory block propagating therefrom to said logic circuit is substantially the same for all of said plurality of memory blocks.

Claim 26

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: a first latch circuit for receiving a first address signal, and delivering said first address signal with a first timing; an input buffer for receiving said first address signal from said first latch circuit and converting said first address signal to a second address signal; a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; at least one internal amplifier for amplifying said second address signal; a logic circuit electrically connected with said memory blocks to receive the output signal of said each memory block for producing a device output signal; and a second latch circuit for receiving said device output signal and delivering said device output signal with a second timing, said first latch circuit, said input buffer, said memory blocks, said at least one internal amplifier, said logic circuit and said second latch circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device, and said at least one internal amplifier being connected to supply said amplified second address signal to any of those of said memory blocks preceded by said internal amplifier as viewed in the direction of said progress of signal processing operations in the integrated circuit device so that said memory blocks preceded by said internal amplifier are connected with said input buffer through said internal amplifier; the length of a conductor for the electrical connection of any one of said memory blocks with said input buffer is smaller than that for the electrical connection of another one of said memory blocks with said input buffer, said another memory block being generally located more distant from said input buffer than said one memory block on said single substrate so that said memory blocks are brought into operation responsive to said second address signal in the ascending order of the lengths of the conductors for the electrical connection of said input buffer with said memory blocks; and the length of a conductor for the electrical connection of said one memory block with said logic circuit is larger than that for the electrical connection of said another memory block with said logic circuit, said one memory block being generally more distant from said logic circuit than said another memory block on said single substrate so that a time necessary for the output signal generated by said one memory block to propagate on the conductor to reach said logic circuit is longer than that for the output signal generated by said another memory block, whereby a sum of a first period of time taken for said second address signal propagating from said input buffer to reach one memory block and a second period of time taken for the output signal of said one memory block propagating therefrom to said logic circuit is substantially the same for all of said plurality of memory blocks.

Claim 27

A semiconductor integrated circuit device according to claim 21, in which said single semiconductor substrate is a semiconductor substrate constituted by one semiconductor chip.

Claim 28

A semiconductor integrated circuit device according to claim 21, in which said single semiconductor substrate is a semiconductor substrate constituted by one semiconductor wafer.

Claim 29

A semiconductor integrated circuit device of claim 21, wherein some of said memory blocks are located a greater distance from said input buffer than others of said memory blocks; and further including a plurality of internal repeating amplifiers between said some memory blocks and said input buffer for amplifying said second address signal and said others of said memory blocks being electrically connected with said input buffer for transferring said second address signal without amplification.

Claim 30

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: an input stage for receiving a first input signal and delivering a second input signal corresponding to said first input signal; a plurality of function blocks each electrically connected with said input stage to operate to generate an output signal responsive to said second input signal; and an output stage electrically connected with said function blocks to receive the output signal of said each function block for producing a device output signal, said input stage, said function blocks and said output stage being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device so that said signals continuously propagate in a direction of said order that is always away from said input stage and toward said output stage to shorten conductor length and propagation time.

Claim 31

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: an input stage for receiving a first input signal and delivering a second input signal corresponding to said first input signal; a plurality of function blocks each electrically connected with said input stage to operate to generate an output signal responsive to said second input signal; and an output stage electrically connected with said function blocks to receive the output signal of said each function block for producing a device output signal, said input stage, said function blocks and said output stage being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device so that said signals continuously propagate in a direction of said order that is always away from said input stage and toward said output stage to shorten conductor length and propagation time.

Claim 32

A semiconductor integrated circuit device of claim 25, as a semiconductor memory device, wherein: the input stage is an input buffer for converting a first address signal as said first input signal to a second address signal as said second input signal; the function blocks are a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; and said output stage is a logic circuit.

Claim 33

A semiconductor integrated circuit device of claim 26, further comprising: at least one internal amplifier for amplifying said second address signal; and said input buffer, said memory blocks, said at least one internal amplifier and said logic circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device, and said at least one internal amplifier being connected to supply said amplified second address signal to only some of said memory blocks preceded by said internal amplifier as viewed in the direction of said progress of signal processing operations in the memory device so that a corresponding some of said memory blocks preceded by said internal amplifier are connected with said input buffer through said internal amplifier.

Claim 34

A semiconductor integrated circuit device of claim 27, further comprising: a first latch circuit for receiving a first address signal, and delivering said first address signal with a first timing to said input buffer; a second latch circuit for receiving said device output signal and delivering said device output signal with a second timing; and said first latch circuit, said input buffer, said memory blocks, said at least one internal amplifier, said logic circuit and said second latch circuit being arranged on said single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device.

Claim 35

A semiconductor integrated circuit device according to claim 28, in which said single semiconductor substrate is a semiconductor substrate constituted by one semiconductor chip.

Claim 36

A semiconductor integrated circuit device according to claim 28, in which said single semiconductor substrate is a semiconductor substrate constituted by one semiconductor wafer.

Claim 37

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: an input stage for receiving a first input signal and delivering at one timing a second input signal corresponding to said first input signal; a plurality of function blocks each electrically connected with said input stage to operate in parallel to generate an output signal responsive to said second input signal and at a plurality of different timings; an output stage electrically connected with said function blocks to receive the output signal of said each function block for producing a device output signal; a plurality of different length first electrical conductors electrically connected between said input stage and respective ones of said function blocks for transmitting said second input stage; and a plurality of repeating amplifier buffers in some of said conductors that are longer than others of said conductors, and the others of said conductors being electrically connected between said input stage and a corresponding one of said function blocks to transmit the second input signal without amplification.

Claim 38

A semiconductor integrated circuit device formed with a single semiconductor substrate, comprising: an input stage for receiving a first input signal and delivering at one timing a second input signal corresponding to said first input signal; a plurality of function blocks each electrically connected with said input stage to operate in parallel to generate an output signal responsive to said second input signal and at a plurality of different timings; an output stage electrically connected with said function blocks to receive the output signal of said each function block for producing a device output signal; a plurality of different length first electrical conductors electrically connected between said input stage and respective ones of said function blocks for transmitting said second input stage; and a plurality of repeating amplifier buffers in some of said conductors that are longer than others of said conductors, and the others of said conductors being electrically connected between said input stage and a corresponding one of said function blocks to transmit the second input signal without amplification.

Claim 39

A semiconductor integrated circuit device of claim 31, further including a plurality of second conductors of different length respectively electrically connected between said output stage and respective ones of said plurality of function blocks to transmit said output signal; and the second electrical conductors that are connected to said some function blocks being of a shorter length than the second electrical conductors connected to said other function blocks for averaging, equalizing and compressing variations of propagation time of the signals from said input stage to said output stage.

Claim 40

A semiconductor integrated circuit device of claim 32, wherein: the input stage is an input buffer for converting a first address signal to a second address signal; the function blocks are a plurality of memory blocks each electrically connected with said input buffer so that each of them delivers an output signal responsive to said second address signal; and said output stage is a logic circuit.

Claim 41

A semiconductor integrated circuit device of claim 31, wherein each repeating amplifier buffer is arranged on the single semiconductor substrate to be sandwiched between and directly electrically connected to at least two of said some of said function blocks.

Claim 42

A semiconductor integrated circuit device of claim 34, further including a plurality of second conductors of different length respectively electrically connected between said output stage and respective ones of said plurality of function blocks to transmit said output signal; and the second electrical conductors that are connected to said some function blocks being of a shorter length than the second electrical conductors connected to said other function blocks for averaging, equalizing and compressing variations of propagation time of the signals from said input stage to said output stage.

Claim 43

A semiconductor integrated circuit device of claim 35 wherein: the input stage is an input buffer for converting a first address signal as the first input signal to a second address signal as the second input signal; the function blocks are a plurality of memory blocks each electrically connected with said input buffer so that each of said function blocks delivers an output signal responsive to said second address signal; and said output stage is a logic circuit.

Claim 44

A semiconductor integrated circuit device of claim 34, wherein: the input stage is an input buffer for converting a first address signal as said first input signal to a second address signal as said second input signal; the function blocks are a plurality of memory blocks each electrically connected with said input buffer so that each of said function blocks delivers an output signal responsive to said second address signal; and said output stage is a logic circuit.

Claim 45

A semiconductor integrated circuit device of claim 31, wherein: the input stage is an input buffer for converting a first address signal as said first input signal to a second address signal as said second input signal; the function blocks are a plurality of memory blocks each electrically connected with said input buffer so that each of said memory blocks delivers an output signal responsive to said second address signal; and said output stage is a logic circuit.