Fuse-programming circuit

Claim 2

An electrical circuit coupled between a first potential and a second potential for providing a programmable voltage level at an output node, comprising: a fuse element having a first terminal coupled to said output node and a second terminal coupled to said first potential; and means for selectively providing a path for passing electrical charge between said second potential and said output node, wherein the path means has substantially infinite resistance between said second potential and said output node when said electrical charge passes through said path means.

Claim 3

An electrical circuit as in claim 1, wherein said path means comprises a first switching means, a second switching means coupled serially to said first switching means, and a capacitive means coupled to a node between said first switching means and said second switching means, and wherein said first switching means is opened when said second switching means closes, and said second switching means is opened when said first switching means closes.

Claim 4

An electrical circuit as in claim 2, wherein said first switching means comprises a first transistor and said second switching means comprises a second transistor, and wherein said electrical circuit further comprising means for generating control signals to switch said first and second transistors.

Claim 5

An electrical circuit as in claim 3, wherein said generating means applies a first control signal to said first transistor and a second control signal, complementary of the first control signal, to said second transistor.

Claim 6

An electrical circuit as in claim 3, wherein said first transistor is of a first type and said second transistor is of a second type opposite to said first type and wherein said control generating means applies one of said control signals to both a control terminal of said first transistor and a control terminal of said second transistor.

Claim 7

An electrical circuit as in claim 5, wherein said first transistor is a p-channel metal-oxide semiconductor transistor and said second transistor is an n-channel metal-oxide semiconductor transistor.

Claim 8

An electrical circuit as in claim 5, wherein said first transistor is an n-channel metal-oxide semiconductor transistor and said second transistor is a p-channel metal-oxide semiconductor transistor.

Claim 9

An electrical circuit as in claim 3, wherein said first and second transistors are metal oxide semiconductor transistors.

Claim 10

An electrical circuit as in claim 2, further comprising means coupled to said output node for improving response time of such electrical circuit, wherein said improving means comprises a driver having an input coupled to said output node and channel means responsive to an output from said driver for providing a conductive path between said second potential and said output node.

Claim 11

An electrical circuit as in claim 9, wherein said driver is an invertor and wherein said channel means is a transistor having a control terminal coupled to an output of said invertor.

Claim 12

An electrical circuit as in claim 2, wherein said second potential is higher than said first potential, and wherein said first and second switching means and said capacitive means operate to supply electrical charge from said second potential to said output node.

Claim 13

An electrical circuit as in claim 2, wherein said second potential is lower than said first potential and wherein said first and second switching means and said capacitive means operate to remove electrical charge from said output node.

Claim 14

In a memory device having an array of memory cells and an array of redundant memory cells, a programming circuit providing a programmable output voltage at an output node for selecting said redundant cells, comprising: a fuse element having a first terminal and a second terminal, said first terminal receiving a first potential and a second terminal coupled to said output node; and means for selectively moving electrical charge between a second potential and said output node, the moving means comprising means for intermediately storing said electrical charge when said electrical charge moves between said second potential and said output node.

Claim 15

In a memory device having an array of memory cells and an array of redundant memory cells, a programming circuit providing a programmable output voltage at an output node for selecting said redundant cells, comprising: a fuse element having a first terminal and a second terminal, said first terminal receiving a first potential and a second terminal coupled to said output node; and means for selectively moving electrical charge between a second potential and said output node, the moving means comprising means for intermediately storing said electrical charge when said electrical charge moves between said second potential and said output node.

Claim 16

A memory device as in claim 13, wherein said storing means comprises a first switch, a second switch, and a capacitor coupled in parallel with one of said first and second switches and wherein said first and second switches open and close in complement of each other.

Claim 17

A memory device as in claim 14, wherein said first switch comprises a first transistor, said second switch comprises a second transistor and wherein said programming circuit further comprises means for generating control signals to switch said first and second transistors.

Claim 18

A memory device as in claim 15, wherein said generating means applies a first control signal to said first transistor, and a second control signal, complementary of the first control signal, to said second transistor.

Claim 19

A memory device as in claim 15, wherein said first transistor is a first type and said second transistor is of a second type, opposite to said first type, and wherein said control generating means applies a control signal to a control terminal of said first transistor and a control terminal of said second transistor.

Claim 20

A memory device as in claim 17, wherein said first transistor is a p-channel metal-oxide semiconductor transistor and said second transistor is an n-channel metal-oxide semiconductor transistor.

Claim 21

A memory device as in claim 17, wherein said first transistor is an n-channel metal-oxide semiconductor transistor and said second transistor is a p-channel metal-oxide semiconductor transistor.

Claim 22

A memory device as in claim 15, wherein said first and second transistors are metal oxide semiconductor transistors.

Claim 23

A memory device as in claim 13, further comprising means coupled to said output node for accelerating response time of such electrical circuit, wherein said accelerating means comprises a driver having an input coupled to said output node and channel means responsive to an output from said driver for providing a conductive path between said second potential and said output node.

Claim 24

A memory device as in claim 21, wherein said driver is an invertor and wherein said channel means is a transistor having a control terminal coupled to an output of said invertor.

Claim 25

A memory device as in claim 14, wherein said second potential is higher than said first potential and wherein said first and second switches and said capacitor operate to intermediately store electrical charge supplied to said output node.

Claim 26

A memory device as in claim 14, wherein said second potential is lower than said first potential and wherein said first and second switches and said capacitor operate to intermediately store electrical charge removed from said output node.

Claim 27

An electrical circuit coupled between a first potential and a second potential for providing a programmable output voltage, comprising: a fuse, a first switch, a second switch, wherein a first terminal of said fuse being connected to a first terminal of said first switch at a first node, wherein one terminal of said second switch being connected to a second terminal of said first switch at a second node, and wherein said second node having a capacitance f or storing electrical charge.

Claim 28

An electrical circuit coupled between a first potential and a second potential for providing a programmable output voltage, comprising: a fuse, a first switch, a second switch, wherein a first terminal of said fuse being connected to a first terminal of said first switch at a first node, wherein one terminal of said second switch being connected to a second terminal of said first switch at a second node, and wherein said second node having a capacitance f or storing electrical charge.

Claim 29

An electrical circuit as in claim 25, wherein said first and second switches open and close in complement of each other.

Claim 30

An electrical circuit as in claim 26, wherein said first switch comprises a first transistor and said second switch comprises a second transistor and wherein said electrical circuit further comprises means for generating signals to switch said first and second transistors.

Claim 31

An electrical circuit as in claim 27, wherein said generating means applies a first signal to said first transistor and a second signal, complementary of the first signal, to said second transistor.

Claim 32

An electrical circuit as in claim 27, wherein said first transistor is of a first type and said second transistor is of a second type, opposite to said first type, and wherein said generating means applies a signal to a control terminal of said first transistor and a control terminal of said second transistor.

Claim 33

An electrical circuit as in claim 29, wherein said first transistor is a p-channel metal-oxide semiconductor transistor and said second transistor is an n-channel metal-oxide semiconductor transistor.

Claim 34

An electrical circuit as in claim 27, wherein said first transistor is an n-channel metal-oxide semiconductor transistor and said second transistor is a p-channel metal-oxide semiconductor transistor.

Claim 35

An electrical circuit as in claim 27, wherein said first and second transistors are metal oxide semiconductor transistors.

Claim 36

An electrical circuit as in claim 25, further comprising means coupled to said output node for accelerating response time of such electrical circuit, wherein said accelerating means comprises a driver having an input coupled to said first node and a channel means responsive to an first from said driver for accelerating a change in voltage at said output node.

Claim 37

An electrical circuit as in claim 33, wherein said driver is an invertor and wherein said channel means is a transistor having a control terminal coupled to an output of said invertor.

Claim 38

An electrical circuit as in claim 25, further comprising a plurality of memory cells, including a set of normal memory cells and a set of redundant memory cells.

Claim 39

In a fuse programming circuit having a fuse coupled to an output node for providing a programmable output voltage at said output node, a method for reducing current consumption in the fuse programming circuit, comprising the steps of: coupling a capacitive element to a voltage source, decoupling said capacitive element from said voltage source, and coupling said capacitive element to said output node, after said decoupling.

Claim 40

In a fuse programming circuit having a fuse coupled to an output node for providing a programmable output voltage at said output node, a method for reducing current consumption in the fuse programming circuit, comprising the steps of: coupling a capacitive element to a voltage source, decoupling said capacitive element from said voltage source, and coupling said capacitive element to said output node, after said decoupling.

Claim 41

A memory device comprising: an array of normal memory cells; an address decoder for selecting a row of normal memory cells in response to an addressing signal; an array of redundant memory cells; a plurality of fuse programming circuits adaptable to provide a control signal representative of a first address of a row of normal memory cells; and a control circuit for disabling the address decoder and selecting a row of redundant memory cells when the addressing signal matches the first address, each fuse programming circuit comprising: a fuse element having a first terminal coupled to the control circuit and a second terminal coupled to a first potential; and means for selectively providing a path for passing electrical charge between a second potential and the control circuit, wherein the path means has substantially infinite resistance between the second potential and the control circuit when said electrical charge passes through said path means.

Claim 42

A memory device comprising: an array of normal memory cells; an address decoder for selecting a row of normal memory cells in response to an addressing signal; an array of redundant memory cells; a plurality of fuse programming circuits adaptable to provide a control signal representative of a first address of a row of normal memory cells; and a control circuit for disabling the address decoder and selecting a row of redundant memory cells when the addressing signal matches the first address, each fuse programming circuit comprising: a fuse element having a first terminal coupled to the control circuit and a second terminal coupled to a first potential; and means for selectively providing a path for passing electrical charge between a second potential and the control circuit, wherein the path means has substantially infinite resistance between the second potential and the control circuit when said electrical charge passes through said path means.

Claim 43

The memory device of claim 37 wherein the control signal representative of the first address is generated by opening at least one fuse element.

Claim 44

In a programmable memory device comprising an array of normal memory cells, an address decoder for selecting a row of normal memory cells in response to an addressing signal, an array of redundant memory cells, a plurality of fuse programming circuits adaptable to provide a control signal representative of a first address of the row of normal memory cells, and a control circuit for disabling the address decoder and selecting a row of redundant memory cells when the addressing signal matches the first address, each fuse programming circuit comprising a fuse element having a first terminal coupled to the control circuit and a second terminal coupled to a first potential, and means for selectively providing a path for passing electrical charge between a second potential and the control circuit, wherein the path means has substantially infinite resistance between the second potential and the control circuit when said electrical charge passes through said path means, a method for programming the device comprising the steps of: detecting a defective row of the normal memory cells; and opening at least one fuse element so that the first address matches the address of the defective row.

Claim 45

In a programmable memory device comprising an array of normal memory cells, an address decoder for selecting a row of normal memory cells in response to an addressing signal, an array of redundant memory cells, a plurality of fuse programming circuits adaptable to provide a control signal representative of a first address of the row of normal memory cells, and a control circuit for disabling the address decoder and selecting a row of redundant memory cells when the addressing signal matches the first address, each fuse programming circuit comprising a fuse element having a first terminal coupled to the control circuit and a second terminal coupled to a first potential, and means for selectively providing a path for passing electrical charge between a second potential and the control circuit, wherein the path means has substantially infinite resistance between the second potential and the control circuit when said electrical charge passes through said path means, a method for programming the device comprising the steps of: detecting a defective row of the normal memory cells; and opening at least one fuse element so that the first address matches the address of the defective row.

Claim 46

An electrical circuit coupled between a first potential and a second potential for providing a programmable voltage level at an output node comprising: a fuse element having a first terminal coupled to said output node and a second terminal coupled to said first potential; and means for selectively providing, in response to a clock signal, a path for passing electrical charge between said second potential and said output node, wherein the path means has substantially infinite resistance between said second potential and said output node when said electrical charge passes through said path means. the path means comprising capacitive means for storing an electrical charge in response to a first state of the clock a clock signal and for providing said electrical charge to said output node in response to a second state of the clock signal.

Claim 47

An electrical circuit coupled between a first potential and a second potential for providing a programmable voltage level at an output node comprising: a fuse element having a first terminal coupled to said output node and a second terminal coupled to said first potential; and means for selectively providing, in response to a clock signal, a path for passing electrical charge between said second potential and said output node, wherein the path means has substantially infinite resistance between said second potential and said output node when said electrical charge passes through said path means. the path means comprising capacitive means for storing an electrical charge in response to a first state of the clock a clock signal and for providing said electrical charge to said output node in response to a second state of the clock signal.