Test pattern signal generator

Claim 2

A test pattern signal generator comprising: a horizontal counter which counts dot clocks and is cleared by a count-up signal that is produced when a horizontal count value reaches a number of dot clocks in a horizontal period; a vertical counter which counts count-up signals of said horizontal counter and is cleared by a count-up signal that is produced when a vertical count value reaches the number of scanning lines in a vertical period; a horizontal memory which is accessed by being addressed by the horizontal count value of said horizontal counter to read out information including a first horizontal signal as a horizontal sync signal and a second horizontal signal which represents a horizontal direction of a test pattern; a vertical memory which is accessed by being addressed by the vertical count value of said vertical counter to read out information including a first vertical signal as a vertical sync signal and a second vertical signal which represents a vertical direction of said test pattern; and an output circuit which produces a test pattern signal on the basis of said second horizontal signal and said second vertical signal.

Claim 3

A test pattern signal generator comprising: a horizontal counter which counts dot clocks and is cleared by a count-up signal that is produced when a horizontal count value reaches a number of dot clocks in a horizontal period; a vertical counter which counts count-up signals of said horizontal counter and is cleared by a count-up signal that is produced when a vertical count value reaches the number of scanning lines in a vertical period; a horizontal memory which is accessed by being addressed by the horizontal count value of said horizontal counter to read out information including a first horizontal signal as a horizontal sync signal, a second horizontal signal which represents a horizontal direction of a test pattern and a third horizontal signal which represents a luminance signal and/or chrominance signal; a vertical memory which is accessed by being addressed by the vertical count value of said vertical counter to read out information including a first vertical signal as a vertical sync signal, a second vertical signal which represents a vertical direction of the test pattern and a third vertical signal which represents a luminance signal and/or chrominance signal; and an output circuit which produces a luminance signal, a chrominance signal and a data signal of the test pattern on the basis of said second horizontal signal, said third horizontal signal, said second vertical signal, and said third vertical signal.

Claim 4

A test pattern signal generator comprising: a horizontal counter which counts dot clocks and is cleared by a count-up signal that is produced when a horizontal count value reaches a number of dot clocks in a horizontal period; a vertical counter which counts count-up signals of said horizontal counter and is cleared by a count-up signal that is produced when a vertical count value reaches the number of scanning lines in a vertical period; a horizontal memory which is accessed by being addressed by the horizontal count value of said horizontal counter to read out information including a first horizontal signal as a horizontal sync signal, a second horizontal signal which represents a horizontal direction of a test pattern and a third horizontal signal which represents a luminance signal and/or chrominance signal; a vertical memory which is accessed by being addressed by the vertical count value of said vertical counter to read out information including a first vertical signal as a vertical sync signal, a second vertical signal which represents a vertical direction of the test pattern and a third vertical signal which represents a luminance signal and/or chrominance signal; and an output circuit which produces a luminance signal, a chrominance signal and a data signal of the test pattern on the basis of said second horizontal signal, said third horizontal signal, said second vertical signal, and said third vertical signal.

Claim 5

A test pattern signal generator according to claim 1 or 2, wherein said horizontal memory stores data indicative of a data display range in the horizontal direction and said vertical memory stores data indicative of the data display range in the vertical direction.

Claim 6

A test pattern signal generator according to claim 3 further comprising: a frequency divider which divides a frequency of said dot clocks and supplies resulting dot clocks to said horizontal counter; and an IC device which operates to narrow a valid period of a signal representative of a data display range in the horizontal direction read out of said horizontal memory.

Claim 7

An apparatus as claimed in claim 1 wherein said output circuit comprises: a pattern selection circuit, responsive to said second horizontal signal and said second vertical signal, for selecting a pattern of said test pattern on the basis of said second horizontal signal and said second vertical signal.

Claim 8

An apparatus as claimed in claim 2 wherein said output circuit comprises: a pattern selection circuit, responsive to said second horizontal signal and said second vertical signal, for selecting a pattern of said test pattern on the basis of said second horizontal signal and said second vertical signal.

Claim 9

An apparatus as claimed in claim 6, wherein said output circuit further comprises a luminance/chrominance signal selection circuit directly connected to said vertical memory and said horizontal memory for selecting luminance and/or chrominance of said test pattern on the basis of said third horizontal signal and said third vertical signal.