US4414567A
Expired / Lapsed
US
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Pattern generating circuit
Assignee: United States Department of the Navy
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Filing: 1981-09-24
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Granted: 1983-11-08
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Expires: 2001-09-24
Abstract
Abstract A pattern generating circuit is disclosed for providing a fixed test pattern to be broadcast on a video display system such that an individual may test or repair the aforementioned video display system. The pattern generating circuit provides a horizontal sync signal, a vertical sync signal, and first and second video component signals which are then summed by a summing amplifier to form a video signal. The horizontal and vertical sync signals are then supplied to the video display system so as to activate the same. This, in turn, allows the video display system, upon receiving the video signal, to broadcast on its display screen the fixed test pattern.
Inventors
- 👤 Herbert Berke
- 👤 Joseph Portoghese
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:07
CPC Classifications
H; H04; H04N; H04N17/00; H04N17/04; H04N17/045
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
392 words
A pattern generating circuit for a one thousand line display comprising, in combination: means having an output, for generating a horizontal sync signal, said horizontal sync signal having a series of uniformly spaced pulses of a first predetermined frequency of 33 kilohertz; means having an input connected to the output of said horizontal sync signal generating means, and an output, for producing, in response to said horizontal sync signal, a first video component signal having a series of uniformly spaced pulses of a second predetermined frequency, said second frequency selected to provide a particular horizontal spacing in said pattern; a one-shot multivibrator having an input connected to the output of said first video component signal producing means and an output, for deriving a pulse suitable for generating narrow vertical lines from each pulse of said first video component signal; means having an input connected to the output of said horizontal sync signal generating means and an output, for producing, in response to said horizontal sync signal, a second video component signal having a series of uniformly spaced pulses of a third predetermined frequency, said third frequency selected to provide vertical spacing equivalent to said horizontal spacing; said second video component signal producing means comprising: a counter having an input connected to the output of said horizontal sync signal genrating means, and an output; a first NAND gate having first and second inputs connected to the output of said counter, and an output; a second NAND gate having first and second inouts and an output, with the first input thereof connected to the output of said horizontal sync signal generating means; a flip-flop having a set input connected to the output of said first NAND gate, a reset input connected to the output of said second NAND GATE, and a Q output connected to the second input of said second NAND gate; means having an input and an output, with the input thereof connected to the output of said multivibrator and the output of said second video component signal producing means, for summing said first and second video component signals so as to provide at the output thereof a video signal; and means having an input connected to the output of said horizontal sync signal generating means and an output, for producing, in response to said horizontal sync signal, a vertical sync signal.
Claim 2
Dependent Claim
392 words
A pattern generating circuit for a one thousand line display comprising, in combination: means having an output, for generating a horizontal sync signal, said horizontal sync signal having a series of uniformly spaced pulses of a first predetermined frequency of 33 kilohertz; means having an input connected to the output of said horizontal sync signal generating means, and an output, for producing, in response to said horizontal sync signal, a first video component signal having a series of uniformly spaced pulses of a second predetermined frequency, said second frequency selected to provide a particular horizontal spacing in said pattern; a one-shot multivibrator having an input connected to the output of said first video component signal producing means and an output, for deriving a pulse suitable for generating narrow vertical lines from each pulse of said first video component signal; means having an input connected to the output of said horizontal sync signal generating means and an output, for producing, in response to said horizontal sync signal, a second video component signal having a series of uniformly spaced pulses of a third predetermined frequency, said third frequency selected to provide vertical spacing equivalent to said horizontal spacing; said second video component signal producing means comprising: a counter having an input connected to the output of said horizontal sync signal genrating means, and an output; a first NAND gate having first and second inputs connected to the output of said counter, and an output; a second NAND gate having first and second inouts and an output, with the first input thereof connected to the output of said horizontal sync signal generating means; a flip-flop having a set input connected to the output of said first NAND gate, a reset input connected to the output of said second NAND GATE, and a Q output connected to the second input of said second NAND gate; means having an input and an output, with the input thereof connected to the output of said multivibrator and the output of said second video component signal producing means, for summing said first and second video component signals so as to provide at the output thereof a video signal; and means having an input connected to the output of said horizontal sync signal generating means and an output, for producing, in response to said horizontal sync signal, a vertical sync signal.
Claim 3
Dependent Claim
164 words
The circuit of claim 1, wherein said summing means comprises: a ground; a first switch having first, second, and third terminals, the first terminal of which is connected to the output of said pulse width expanding means, and the second terminal of which is connected to said ground; a second switch having first, second, and third terminals, the first terminal of which is connected to the output of said second video component signal producing means, and the second terminal of which is connected to said ground; an operational amplifier having a negative input connected to the third terminal of said first switch and the third terminal of said second switch, a positive input connected to said ground, and an output; a first diode having an anode connected to the negative input of said operational amplifier, and a cathode; and a second diode having an anode connected to the cathode of said first diode, and a cathode connected to the output of said operational amplifier.
Claim 4
Dependent Claim
15 words
The circuit of claim 1, wherein said vertical sync signal producing means comprises a counter.
Claim 5
Dependent Claim
81 words
The circuit of claim 1, further characterized by a video display having a display screen, a first input connected to the output of said horizontal sync signal generating means, a second input connected to the outut of said summing means, and a third input connected to the output of said vertical sync signal producing means, said video display system being adapted for broadcasting on the screen thereof a test pattern, in response to said horizontal sync, vertical sync, and video signals.
Claim 6
Dependent Claim
291 words
A circuit for generating a test pattern for a one thousand line display comprising, in combination: a master clock signal generator having an output of 33 kHz; a phase lock loop circuit having an input connected to the output of said master clock signal generator, and an output; a one-shot multivibrator having an input connected to the output of said phase lock loop circuit, and an output; a ground; a first switch having first, second, and third terminals, the first terminal of which is connected to the output of said one-shot multivibrator, and the second terminal of which is connected to said ground; a first counter having an input connected to the output of said master clock signal generator, and an output; a second counter having an input connected to the output of said master clock signal generator, and an output; a first NAND gate having first and second inputs connected to the output of said first counter, and an output; a second NAND gate having first and second inputs and an output, with the first input thereof connected to the output of said master clock signal generator; a flip-flop havng a set input, a reset input, and a Q output, with the set input thereof connected to the output of said first NAND gate, with the reset input thereof connected to the output of said second NAND gate, and with the Q output thereof connected to the second input of said second NAND gate; a second switch having first, second, and third terminals, with the first terminal thereof connected to said ground; and a summing amplifier having a negative input connected to the outputs of said first and second switches, a positive input connected to said ground, and an output.
Claim 7
Dependent Claim
291 words
A circuit for generating a test pattern for a one thousand line display comprising, in combination: a master clock signal generator having an output of 33 kHz; a phase lock loop circuit having an input connected to the output of said master clock signal generator, and an output; a one-shot multivibrator having an input connected to the output of said phase lock loop circuit, and an output; a ground; a first switch having first, second, and third terminals, the first terminal of which is connected to the output of said one-shot multivibrator, and the second terminal of which is connected to said ground; a first counter having an input connected to the output of said master clock signal generator, and an output; a second counter having an input connected to the output of said master clock signal generator, and an output; a first NAND gate having first and second inputs connected to the output of said first counter, and an output; a second NAND gate having first and second inputs and an output, with the first input thereof connected to the output of said master clock signal generator; a flip-flop havng a set input, a reset input, and a Q output, with the set input thereof connected to the output of said first NAND gate, with the reset input thereof connected to the output of said second NAND gate, and with the Q output thereof connected to the second input of said second NAND gate; a second switch having first, second, and third terminals, with the first terminal thereof connected to said ground; and a summing amplifier having a negative input connected to the outputs of said first and second switches, a positive input connected to said ground, and an output.
Claim 8
Dependent Claim
12 words
The circuit of claim 5, wherein said flip-flop comprises a JK flip-flop.
Claim 9
Dependent Claim
13 words
The circuit of claim 5, wherein said summing amplifier comprises an operational amplifier.
Claim 10
Dependent Claim
64 words
The circuit of claim 5, further characterized by a first diode having a cathode and an anode, with the anode thereof connected to the negative input of said summing amplifier; and a second diode having a cathode and an anode, with the anode thereof connected to the cathode of said first diode, and the cathode thereof connected to the output of said summing amplifier.
Claim 11
Dependent Claim
69 words
The circuit of claim 5, further characterized by a video display system having a horizontal sync input, a vertical sync input, and a video input, with the horizontal sync input thereof connected to the output of said master clock signal generator, with the vertical sync input thereof connected to the output of said second counter, and with the video input thereof connected to the output of said operational amplifier.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-07 | 1987-05-09 | 1987-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-07 | 1991-05-09 | 1991-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-07 | 1995-05-09 | 1995-11-08 | $7700.00 | Window Closed / Lapsed |