US5319253A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data retention mode control circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-12-02
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Granted: 1994-06-07
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Expires: 2012-12-02
Abstract
Abstract A semiconductor memory device with data retention function to retain data is provided with a sense amplifier control signal generating circuit comprising a switching circuit controlled by a data retention mode detection signal so as to make the time interval between enabling of a word line and starting of an N- or P-type sense amplifier longer in data retention mode than in normal mode. Thus the inventive circuit generates a sense amplifier control signal whose delay time differs in the normal and data retention modes, so that the data retention mode is performed without influencing the operational speed, the charge sharing is sufficiently achieved in the data retention mode, and the direct current flowing is prevented.
Inventors
- 👤 Jei-Hwan You
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:45
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/22; G11C7/06; G11C7/065; H; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
220 words
In a semiconductor memory device having a data retention function to retain data, a sense amplifier control signal generating circuit comprising: an N-type sense amplifier control signal means for generating an N-type signal, said N-type sense amplifier control signal means comprising: a first normal mode enable circuit; and, a first data retention mode enable circuit comprising: a first switching circuit controlled by a data retention mode detection signal for making a time interval between enabling of a word line and starting of said N-type sense amplifier control signal means longer in data retention mode than in normal mode; and, a first delay means comprising at least one inverter for delaying an output of said first switching circuit; a P-type sense amplifier control signal means for generating a P-type signal dependent on said N-type signal; said P-type sense amplifier control signal means comprising: a second normal mode enable circuit; and, a second data retention mode enable circuit comprising: a second switching circuit controlled by said data retention mode detection signal for making a time interval between enabling of said word line and starting of said P-type sense amplifier control signal means longer in said data retention mode than in said normal mode; and, a second delay means comprising at least one inverter for delaying an output of said second switching circuit.
Claim 2
Dependent Claim
220 words
In a semiconductor memory device having a data retention function to retain data, a sense amplifier control signal generating circuit comprising: an N-type sense amplifier control signal means for generating an N-type signal, said N-type sense amplifier control signal means comprising: a first normal mode enable circuit; and, a first data retention mode enable circuit comprising: a first switching circuit controlled by a data retention mode detection signal for making a time interval between enabling of a word line and starting of said N-type sense amplifier control signal means longer in data retention mode than in normal mode; and, a first delay means comprising at least one inverter for delaying an output of said first switching circuit; a P-type sense amplifier control signal means for generating a P-type signal dependent on said N-type signal; said P-type sense amplifier control signal means comprising: a second normal mode enable circuit; and, a second data retention mode enable circuit comprising: a second switching circuit controlled by said data retention mode detection signal for making a time interval between enabling of said word line and starting of said P-type sense amplifier control signal means longer in said data retention mode than in said normal mode; and, a second delay means comprising at least one inverter for delaying an output of said second switching circuit.
Claim 3
Dependent Claim
217 words
A sense amplifier control signal generating circuit receiving a word line signal and comprising an N-type sense amplifier control signal generator (100) and a P-type sense amplifier control signal generator (200), said generating circuit comprising: said N-type sense amplifier control signal generator (100) comprising; a first enable circuit (100A) with a first delay means for delaying said word line signal for a given time; a second enable circuit (100B) for delaying said word line signal and provided with a first switching circuit (35) controlled by a data retention mode detection signal (φDR); and a first output means (39-41) for performing a logical operation on the output signals of said first and second enable circuits (100A, 100B) to generate an N-type sense amplifier control signal; and said P-type sense amplifier control signal generator (200) comprising; a third enable circuit (200A) with a second delay means for delaying said N-type amplifier control signal for a given time; a fourth enable circuit (200B) for delaying said N-type sense amplifier control signal and provided with a second switching circuit (55) controlled by said data retention mode detection signal (φDR); and a second output means (59-60) for performing a logical operation on the output signals of said third and fourth enable circuits (200A, 200B) to produce a P-type sense amplifier control signal.
Claim 4
Dependent Claim
217 words
A sense amplifier control signal generating circuit receiving a word line signal and comprising an N-type sense amplifier control signal generator (100) and a P-type sense amplifier control signal generator (200), said generating circuit comprising: said N-type sense amplifier control signal generator (100) comprising; a first enable circuit (100A) with a first delay means for delaying said word line signal for a given time; a second enable circuit (100B) for delaying said word line signal and provided with a first switching circuit (35) controlled by a data retention mode detection signal (φDR); and a first output means (39-41) for performing a logical operation on the output signals of said first and second enable circuits (100A, 100B) to generate an N-type sense amplifier control signal; and said P-type sense amplifier control signal generator (200) comprising; a third enable circuit (200A) with a second delay means for delaying said N-type amplifier control signal for a given time; a fourth enable circuit (200B) for delaying said N-type sense amplifier control signal and provided with a second switching circuit (55) controlled by said data retention mode detection signal (φDR); and a second output means (59-60) for performing a logical operation on the output signals of said third and fourth enable circuits (200A, 200B) to produce a P-type sense amplifier control signal.
Claim 5
Dependent Claim
24 words
A sense amplifier control signal generating circuit as claimed in claim 2, wherein said first and second delay means comprise at least one inverter.
Claim 6
Dependent Claim
38 words
A sense amplifier control signal generating circuit as claimed in claim 2, wherein only said first and third enable circuits are enabled in normal mode, and said first to fourth enable circuits are enabled in data retention mode.
Claim 7
Dependent Claim
28 words
A sense amplifier control signal generating circuit as claimed in claim 2, wherein the outputs of said second and fourth enable circuits are enabled in data retention mode.
Claim 8
Dependent Claim
40 words
A sense amplifier control signal generating circuit as claimed in claim 2, wherein said first and second output means comprise a NOR gate, and said logical operation of said first and second output means is performed by said NOR gate.
Claim 9
Dependent Claim
194 words
A sense amplifier control signal generating circuit comprising a first-type sense amplifier control signal generator and a second-type sense amplifier control signal generator, said generating circuit comprising: said first-type sense amplifier control signal generator comprising; a first enable circuit with a first delay means for delaying a given input signal for a given time; a second enable circuit for delaying said input signal and provided with a first switching circuit controlled by a data retention mode detection signal (φDR); and a first output means for performing a logical operation on the output signals of said first and second enable circuits to generate a first-type sense amplifier control signal; and said second-type sense amplifier control signal generator comprising; a third enable circuit with a second delay means for delaying said first-type amplifier control signal for a given time; a fourth enable circuit for delaying said first-type sense amplifier control signal and provided with a second switching circuit controlled by said data retention mode detection signal (φDR); and a second output means for performing a logical operation on the output signals of said third and fourth enable circuits to produce a second-type sense amplifier control signal.
Claim 10
Dependent Claim
194 words
A sense amplifier control signal generating circuit comprising a first-type sense amplifier control signal generator and a second-type sense amplifier control signal generator, said generating circuit comprising: said first-type sense amplifier control signal generator comprising; a first enable circuit with a first delay means for delaying a given input signal for a given time; a second enable circuit for delaying said input signal and provided with a first switching circuit controlled by a data retention mode detection signal (φDR); and a first output means for performing a logical operation on the output signals of said first and second enable circuits to generate a first-type sense amplifier control signal; and said second-type sense amplifier control signal generator comprising; a third enable circuit with a second delay means for delaying said first-type amplifier control signal for a given time; a fourth enable circuit for delaying said first-type sense amplifier control signal and provided with a second switching circuit controlled by said data retention mode detection signal (φDR); and a second output means for performing a logical operation on the output signals of said third and fourth enable circuits to produce a second-type sense amplifier control signal.
References Cited (Backward Citations)
US5033026A
Cited
US5206830A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |