Pseudo-static random access memory

Claim 1

A semiconductor memory comprising: a plurality of dynamic memory cells arrayed in a matrix of rows and columns and connected to word lines in rows and bit lines in columns, a plurality of address terminals receiving row address signals, a row decoder responsive to the row address signal received by said address terminals for selecting one of said word lines thereby allowing memory cells connected to the selected word line to produce data stored therein to corresponding bit lines in response to a first timing signal, a plurality of sense amplifiers coupled to said bit lines, respectively, said sense amplifiers amplifying data read-out to said bit lines, from the memory cells connected to the selected word line, in response to a second timing signal, a refresh signal terminal receiving a refresh signal having active and inactive levels, means for self-refreshing rows of said memory cells in said matrix in a self-refreshing mode when said refresh signal is at the active level, said self-refreshing means including means for internally producing row address signals to designate rows to be subjected to the self-refreshing, said self-refreshing means further comprising means coupled to said refresh signal terminal for generating a control signal of a first level representing the self-refreshing mode when said refresh signal is at the active level and a control signal of a second level when said refresh signal is at the inactive level, and a timing signal generator generating said first timing signal and said second timing signal after generation of said first timing signal , said timing signal generator generating said second timing signal after a first delay time from generation of said first timing signal when said control signal is at the first level and after a second delay time which is shorter than said first delay time from the generation of said first timing signal when said control signal is at the second level.