US5318922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing a semiconductor device
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-02-11
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Granted: 1994-06-07
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Expires: 2013-02-11
Abstract
Abstract A device isolation method for use in a process for manufacturing a semiconductor device, in which a pad oxide layer and a nitride layer are sequentially formed on the surface of a semiconductor substrate, an opening for defining the device isolating region is formed, and the substrate is oxidized at a high temperature to form a field oxide layer. Before the field oxide layer is formed, the nitride layer and pad oxide layer are etched to form a nitride layer spacer on the sidewalls of the pad oxide layer, to suppress the creation of a bird's beak due to lateral diffusion of oxygen between the pad oxide layer and nitride layer. In one embodiment, the nitride layer spacer is formed while leaving part of the pad oxide layer on the substrate, and the lower periphery of the spacer is undercut to be filled with an oxidizable material, thereby minimizing lateral diffusion of oxygen during the oxidation step.
Inventors
- 👤 Byung-hak Lim
- 👤 Yang-goo Lee
- 👤 Seon-jun Kim
- 👤 Dong-gun Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:34
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/10; H10W10/13; H10P; H10P14/00; H10P14/60; H10P14/61; H10W10/0125; H10W10/0126
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
318 words
A method for manufacturing a semiconductor device, comprising the steps of: forming a buffer layer on a semiconductor substrate having device active regions and a device isolating region disposed between said device active regions, said device active regions and said device isolating region being co-planar; forming a first oxidation resistant layer on said buffer layer; selectively removing a portion of said first oxidation resistant layer disposed above said device isolating region, with remaining portions of said first oxidation resistant layer being disposed above said device active regions, with opposed sidewalls of said first oxidation resistant layer defining an opening in said first oxidation resistant layer above said device isolating region, and with a portion of said buffer layer disposed above said device isolating region being exposed by said opening; forming a spacer made of oxidation-resistant material on each of said opposed sidewalls of said first oxidation resistant layer; isotopically etching said exposed portion of said buffer layer in such a manner as to etch away both said exposed portion of said buffer layer and a portion of said buffer layer disposed beneath a marginal edge portion of a bottom surface of each said spacer, to thereby form a cavity beneath each said spacer, wherein each said cavity extends beneath a corresponding one of said spacers in a lateral direction towards a vertical plane defined by a corresponding one of said opposed sidewalls of said first oxidation resistant layer, but not s far as said vertical plane; depositing an oxidizable material on the overall structure resulting from the preceding steps in such a manner as to fill said cavity beneath each said spacer with said oxidizable material, to thereby provide an oxidizable material layer; and, oxidizing said oxidizable material layer in such a manner as to form a field oxide layer in said device isolating region, and a peripheral oxide layer adjacent opposite sides of said device isolating region.
Claim 2
Independent Claim
318 words
A method for manufacturing a semiconductor device, comprising the steps of: forming a buffer layer on a semiconductor substrate having device active regions and a device isolating region disposed between said device active regions, said device active regions and said device isolating region being co-planar; forming a first oxidation resistant layer on said buffer layer; selectively removing a portion of said first oxidation resistant layer disposed above said device isolating region, with remaining portions of said first oxidation resistant layer being disposed above said device active regions, with opposed sidewalls of said first oxidation resistant layer defining an opening in said first oxidation resistant layer above said device isolating region, and with a portion of said buffer layer disposed above said device isolating region being exposed by said opening; forming a spacer made of oxidation-resistant material on each of said opposed sidewalls of said first oxidation resistant layer; isotopically etching said exposed portion of said buffer layer in such a manner as to etch away both said exposed portion of said buffer layer and a portion of said buffer layer disposed beneath a marginal edge portion of a bottom surface of each said spacer, to thereby form a cavity beneath each said spacer, wherein each said cavity extends beneath a corresponding one of said spacers in a lateral direction towards a vertical plane defined by a corresponding one of said opposed sidewalls of said first oxidation resistant layer, but not s far as said vertical plane; depositing an oxidizable material on the overall structure resulting from the preceding steps in such a manner as to fill said cavity beneath each said spacer with said oxidizable material, to thereby provide an oxidizable material layer; and, oxidizing said oxidizable material layer in such a manner as to form a field oxide layer in said device isolating region, and a peripheral oxide layer adjacent opposite sides of said device isolating region.
Claim 3
Dependent Claim
37 words
The method as set forth in claim 1, further comprising the step of removing each said spacer, said remaining portions of said first oxidation resistant layer, remaining portions of said buffer layer, and said peripheral oxide layer.
Claim 4
Dependent Claim
17 words
The method as set forth in claim 1, wherein said buffer layer is a pad oxide layer.
Claim 5
Dependent Claim
26 words
The method as set forth in claim 1, wherein said buffer layer is a composite layer comprised of a pad oxide layer and a polysilicon layer.
Claim 6
Dependent Claim
19 words
The method as set forth in claim 1, wherein said first oxidation resistant layer is a silicon nitride layer.
Claim 7
Dependent Claim
70 words
The method as set forth in claim 1, wherein said forming a spacer step is carried out by forming a second oxidation resistant layer on said remaining portions of said first oxidation resistant layer and said exposed portion of said buffer layer and then anisotropically etching said second oxidation resistant layer in such a manner as to form said spacers on said opposed sidewalls of said first oxidation resistant layer.
Claim 8
Dependent Claim
27 words
The method as set forth in claim 1, wherein said oxidizable material is made of a material selected from the group consisting of amorphous silicon and polysilicon.
Claim 9
Dependent Claim
50 words
The method as set forth in claim 1, further comprising, prior to execution of said oxidizing step, the step of implanting impurities through said opening in said first oxidation resistant layer into said device isolating region of said substrate, to thereby form a channel-stop layer in said device isolating region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-06 | 1997-12-06 | 1998-06-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-06 | 2001-12-06 | 2002-06-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-06 | 2005-12-06 | 2006-06-07 | $7700.00 | Window Closed / Lapsed |