Data processor for detecting identical data coexisting in a plurality of data section of data transmission paths

Claim 2

A data processor comprising: a pre-detecting portion; said pre-detecting portion including, a data detecting means, having a plurality of parallel input ports and a plurality of data transmission paths, each of a plurality of stages, subsequent to the input ports, for detecting a time period in which data exist for each of the data transmission paths, comparing and determining means for comparing identifiers, each identifier being at least a part of the data, during a time period in which data are detected by said data detecting means in each of the data transmission paths, and flag generating means for generating a flag indicating a match of identifiers for the data on each of the data transmission paths and access contention in a matching memory based on a result of the comparison obtained by said comparing and determining means, for detecting in advance said access contention, for maintaining the data on each of the data transmission paths, and for adding said flag to the maintained data; and a template matching portion, wherein said template matching portion includes data transmission paths, each having one or more input ports corresponding to outputs of said pre-detecting portion and capable performing in a pipeline processing mode, a matching memory having addresses corresponding to the identifiers of the data in which one or more identifiers are allocated to one address when a number of identifiers is larger than a number of the addresses, memory access control means for arbitrating data transmission such that accesses to said matching memory are not simultaneously made with respect to at least one data transmission path, access being made in the order from reading and writing data not being read out until writing of previous data is terminated, coincidence determining means for determining data queuing in said matching memory according to a priority added in advance to an identifier of the data when access contention occurs in said matching memory, and data processing means for replacing data in said matching memory, combining data or erasing data in said matching memory based on a result of the determination by said coincidence determining means such that pipeline processing of respective data is performed in parallel with respect to an input of data on at least one parallel data transmission paths and template matching is performed at high speed.

Claim 3

The data processor of claim 1, further including, coexistence detecting means for detecting a common period in the time periods during which data is detected on two of the plurality of data transmission paths, said comparing and determining means comparing during said common period.

Claim 4

The data processor of claim 2, wherein a number of the plurality of stages of the data transmission paths are made coincident with each other such that a time period for comparing by the comparing means becomes equal to the time period originally detected by the data detecting means to ensure accurate subsequent processing.

Claim 5

The data processor of claim 1, wherein the data transmission paths are each of a same directionality such that existing data on each of the transmission paths proceed in a single, common direction.

Claim 6

A data processor comprising: a plurality of data transmission paths for transmitting data in packets; a matching memory having at least one input port connected to the data transmission paths and at least one address corresponding to an identifier, said identifier being at least a part of inputted from the input port, the matching memory including, first memory reading means for detecting presence of a flag in a data packet on one of the data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path, and maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path, second memory reading means for, upon the first memory reading means failing to detect the presence of a flag in the data packet, reading previously stored data from said matching memory according to the address corresponding to said identifier of the input data; comparing and determining means for comparing the previously stored data read out from said matching memory by said second memory reading means with the input data; data processing means for processing each data based on a result on the comparison and for, if the first memory reading means detects presence of the flag in the data packet, combining the data packet on the one transmission path with the data packet on the other transmission path for subsequent output; memory writing means for writing a result of the processing by said data processing means into said matching memory at the address corresponding to said identifier of the data; and memory access control means for arbitrating data transmission on said data transmission paths to prevent simultaneous accesses to said matching memory with respect to two or more data packets transmitted on the data transmission paths, such that respective data are processed in a parallel pipeline manner and template matching is performed at high speed.

Claim 7

A data processor comprising: a plurality of data transmission paths for transmitting data in packets; a matching memory having at least one input port connected to the data transmission paths and at least one address corresponding to an identifier, said identifier being at least a part of inputted from the input port, the matching memory including, first memory reading means for detecting presence of a flag in a data packet on one of the data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path, and maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path, second memory reading means for, upon the first memory reading means failing to detect the presence of a flag in the data packet, reading previously stored data from said matching memory according to the address corresponding to said identifier of the input data; comparing and determining means for comparing the previously stored data read out from said matching memory by said second memory reading means with the input data; data processing means for processing each data based on a result on the comparison and for, if the first memory reading means detects presence of the flag in the data packet, combining the data packet on the one transmission path with the data packet on the other transmission path for subsequent output; memory writing means for writing a result of the processing by said data processing means into said matching memory at the address corresponding to said identifier of the data; and memory access control means for arbitrating data transmission on said data transmission paths to prevent simultaneous accesses to said matching memory with respect to two or more data packets transmitted on the data transmission paths, such that respective data are processed in a parallel pipeline manner and template matching is performed at high speed.

Claim 8

A data processor comprising: data transmission paths for transmitting data packets; a matching memory having at least one input port connected to the data transmission paths and at least one address corresponding to an identifier, said identifier being at least a part of a data packet having word data, inputted from one of the data transmission paths through the input port, the matching memory including, first memory reading means for detecting presence of a flag in a data packet on one of the data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path, and maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path, second memory reading means for, upon the first memory means failing to detect the presence of a flag in the data packet, reading previously stored data from said matching memory located at the address corresponding to said identifier of the input data packet; comparing and determining means for comparing the read data with said identifier of the input data packet and for determining a relationship therebetween; data processing means for combining the data packet on the one transmission path with the data packet on the other transmission path upon the first memory reading means detecting presence of the flag, for processing the data and for combining contents of the inputted data and the read data for subsequent output based upon the first memory reading means failing to detect the presence of the flag and upon the comparison obtained by said comparing and determining means being a match, and for determining priority between the input and read data upon the first memory reading means failing to detect the presence of the flag and upon the comparison obtained by the comparing and determining means failing to indicate a match; memory writing means for writing data processed by said data processing means, with the highest relative determined priority, into said matching memory at the address corresponding to said identifier of the data packet upon the data processing means determining priority; and memory access control means for arbitrating data transmission on said data transmission paths to prevent simultaneous accesses to said matching memory with respect to two or more data packets transmitted on the data transmission paths such that respective data are processed in a parallel pipeline manner and template matching is performed at high speed.

Claim 9

A data processor comprising: data transmission paths for transmitting data packets; a matching memory having at least one input port connected to the data transmission paths and at least one address corresponding to an identifier, said identifier being at least a part of a data packet having word data, inputted from one of the data transmission paths through the input port, the matching memory including, first memory reading means for detecting presence of a flag in a data packet on one of the data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path, and maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path, second memory reading means for, upon the first memory means failing to detect the presence of a flag in the data packet, reading previously stored data from said matching memory located at the address corresponding to said identifier of the input data packet; comparing and determining means for comparing the read data with said identifier of the input data packet and for determining a relationship therebetween; data processing means for combining the data packet on the one transmission path with the data packet on the other transmission path upon the first memory reading means detecting presence of the flag, for processing the data and for combining contents of the inputted data and the read data for subsequent output based upon the first memory reading means failing to detect the presence of the flag and upon the comparison obtained by said comparing and determining means being a match, and for determining priority between the input and read data upon the first memory reading means failing to detect the presence of the flag and upon the comparison obtained by the comparing and determining means failing to indicate a match; memory writing means for writing data processed by said data processing means, with the highest relative determined priority, into said matching memory at the address corresponding to said identifier of the data packet upon the data processing means determining priority; and memory access control means for arbitrating data transmission on said data transmission paths to prevent simultaneous accesses to said matching memory with respect to two or more data packets transmitted on the data transmission paths such that respective data are processed in a parallel pipeline manner and template matching is performed at high speed.

Claim 10

A data processing method comprising the steps of: (a) detecting a time period in which data exists in each of a plurality of data transmission paths, each of a plurality of stages; (b) comparing identifiers, each identifier being at least a part of the data, during a time period in which data are detected in said step (a) in each of the data transmission paths; (c) generating a flag indicating a match of identifiers for the data between the data transmission paths and access contention in a matching memory based on a result of the comparison obtained in said step (b); (d) detecting, in advance, the access contention; (e) maintaining the data on each of the data transmission paths; and (f) adding the flag to the maintained data; (g) arbitrating data transmission such that accesses to a matching memory are not simultaneously made with respect to at least one data transmission path, access is being made in the order from reading and writing data not being read out until writing of previous data is terminated; (h) determining data queuing in the matching memory according to a priority added in advance to an identifier of the data when access contention occurs in the matching memory; and (i) replacing data in the matching memory by combining data or erasing data in the matching memory based on a result of the determination in said step (h) such that pipeline processing of respective data is performed in parallel with respect to an input of data on at least one parallel data transmission path and template matching is performed at high speed.

Claim 11

A data processing method comprising the steps of: (a) detecting a time period in which data exists in each of a plurality of data transmission paths, each of a plurality of stages; (b) comparing identifiers, each identifier being at least a part of the data, during a time period in which data are detected in said step (a) in each of the data transmission paths; (c) generating a flag indicating a match of identifiers for the data between the data transmission paths and access contention in a matching memory based on a result of the comparison obtained in said step (b); (d) detecting, in advance, the access contention; (e) maintaining the data on each of the data transmission paths; and (f) adding the flag to the maintained data; (g) arbitrating data transmission such that accesses to a matching memory are not simultaneously made with respect to at least one data transmission path, access is being made in the order from reading and writing data not being read out until writing of previous data is terminated; (h) determining data queuing in the matching memory according to a priority added in advance to an identifier of the data when access contention occurs in the matching memory; and (i) replacing data in the matching memory by combining data or erasing data in the matching memory based on a result of the determination in said step (h) such that pipeline processing of respective data is performed in parallel with respect to an input of data on at least one parallel data transmission path and template matching is performed at high speed.

Claim 12

The data processing method of claim 7, further including the step of; (g) detecting a common period in the time periods during which data is detected on two of the plurality of data transmission paths, said comparing of step (b) occurring during the common period.

Claim 13

The data processing method of claim 8, wherein a number of the plurality of stages of the data transmission paths are made coincident with each other such that a time period for comparing in step (b) becomes equal to the time period originally detected in step (a) to ensure accurate subsequent processing.

Claim 14

The data processing method of claim 7, wherein the data transmission paths are each of a same directionality such that existing data on each of the transmission paths proceeds in a single, common direction.

Claim 15

A data processing method, comprising the steps of: (a) detecting presence of a flag in a data packet on one of a plurality of data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path; (b) maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path; (c) reading, upon said step (a) failing to detect the presence of a flag in the data packet, previously stored data from a matching memory according to the address corresponding to the identifier of the input data; (d) comparing the previously stored data read out from the matching memory in said step (c) with the input data; (e) processing each data based on a result on the comparison; (f) combining, if presence of the flag is detected in the data packet in said step (a), the data packet on the one transmission path with the data packet on the other transmission path for subsequent output; (g) writing a result of the processing of said step (e) into the matching memory at the address corresponding to the identifier of the data; and (h) arbitrating data transmission on the data transmission paths to prevent simultaneous accesses to the matching memory with respect to two or more data packets transmitted on the data transmission paths, such that respective data are processed in a parallel pipeline manner and template matching is performed at high speed.

Claim 16

A data processing method, comprising the steps of: (a) detecting presence of a flag in a data packet on one of a plurality of data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path; (b) maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path; (c) reading, upon said step (a) failing to detect the presence of a flag in the data packet, previously stored data from a matching memory according to the address corresponding to the identifier of the input data; (d) comparing the previously stored data read out from the matching memory in said step (c) with the input data; (e) processing each data based on a result on the comparison; (f) combining, if presence of the flag is detected in the data packet in said step (a), the data packet on the one transmission path with the data packet on the other transmission path for subsequent output; (g) writing a result of the processing of said step (e) into the matching memory at the address corresponding to the identifier of the data; and (h) arbitrating data transmission on the data transmission paths to prevent simultaneous accesses to the matching memory with respect to two or more data packets transmitted on the data transmission paths, such that respective data are processed in a parallel pipeline manner and template matching is performed at high speed.

Claim 17

A data processing method, comprising the steps of: (a) detecting presence of a flag in a data packet on one of a plurality of data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path; (b) maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path; (c) reading, upon said step (a) failing to detect the presence of a flag in the data packet, previously stored data from a matching memory located at the address corresponding to the identifier of the input data packet; (d) comparing the read data with the identifier of the input data packet and determining a relationship therebetween; (e) combining the data packet on the one transmission path with the data packet on the other transmission path upon said step (a) detecting presence of the flag; (f) processing the data contents of the inputted data and the read data for subsequent output based upon the failure to detect the presence of the flag in said step (a) and upon the comparison in said step (d) being a match; (g) determining priority between the input and read data upon the failure to detect the presence of the flag in said step (a) and upon the comparison in said step (d) failing to indicate a match; (h) writing data processed in said step (f) with the highest relative determined priority into the matching memory at the address corresponding to the identifier of the data packet, upon the determining of priority in step (g); (i) arbitrating data transmission on the data transmission paths to prevent simultaneous accesses to the matching memory with respect to two or more data packets transmitted on the data transmission paths such that respective data re processed in a parallel pipeline manner and template matching is performed at high speed.

Claim 18

A data processing method, comprising the steps of: (a) detecting presence of a flag in a data packet on one of a plurality of data transmission paths, the flag indicating a data packet on one transmission path with an identifier matching a data packet on another transmission path; (b) maintaining the detected data packet with the flag at a constant point on the transmission path until another data packet with a flag is detected on the other transmission path; (c) reading, upon said step (a) failing to detect the presence of a flag in the data packet, previously stored data from a matching memory located at the address corresponding to the identifier of the input data packet; (d) comparing the read data with the identifier of the input data packet and determining a relationship therebetween; (e) combining the data packet on the one transmission path with the data packet on the other transmission path upon said step (a) detecting presence of the flag; (f) processing the data contents of the inputted data and the read data for subsequent output based upon the failure to detect the presence of the flag in said step (a) and upon the comparison in said step (d) being a match; (g) determining priority between the input and read data upon the failure to detect the presence of the flag in said step (a) and upon the comparison in said step (d) failing to indicate a match; (h) writing data processed in said step (f) with the highest relative determined priority into the matching memory at the address corresponding to the identifier of the data packet, upon the determining of priority in step (g); (i) arbitrating data transmission on the data transmission paths to prevent simultaneous accesses to the matching memory with respect to two or more data packets transmitted on the data transmission paths such that respective data re processed in a parallel pipeline manner and template matching is performed at high speed.